Hi Michal,
On 11/26/20 8:20 PM, Michal Simek wrote:
Hi,
On 26. 11. 20 11:19, quanyang.w...@windriver.com wrote:
From: Quanyang Wang <quanyang.w...@windriver.com>
Hi Bruce,
Would you please help remove the obsolete branch standard/xlnx-soc in
linux-yocto-dev
and apply these patches for v5.10 as below to the new branch standard/xlnx-soc?
There are 1451 patches in this pull request.
Among them, 1443 patches are picked from
https://github.com/Xilinx/linux-xlnx.git xlnx_rebase_v5.4 (tag
xlnx_rebase_v5.4_2020.2).
and some of them are modified to adapt to the v5.10. And there are 4 new
patches.
I took at look at your branch and there are some interesting things.
First of all thanks for your work.
Do you use any script of it because I see you keep references to origin
sha1 which is quite nice?
yes, the script is as below:
---
#!/bin/sh
add_sdk_commit ()
{
for each in `ls *.patch`; do title=`grep -m 1 -n "From " $each`;
echo $title
num=`grep -m 1 -n ^$ $each | awk -F : '{print$1}'`;
commit=`echo $title | cut -c 7-47`;
echo $commit
echo $num
sed "$num a\https://github.com/Xilinx/linux-xlnx.git
xlnx_rebase_v5.4\n" -i $each;
sed "$num a\commit $commit from" -i $each;
done
}
add_sdk_commit
---
Then obviously we need to switch to psgtr mainline driver and add
missing features because that's the only way to go in long run. I tested
yesterday sata and it worked. I expect DP should be also fine and others
needs to be checked. Yesterday I have sent email to Laurent to check
some details about it.
The DP driver can't work in mainline v5.9 and v5.10 now. I tried to make
it work
but failed. I modified the dts (xilinx_dpsub.patch in attachment) to
make the DP driver get through
the initialization but the DP monitor has no signal. I don't know if
this is a DP issue or psgtr phy issue.
So for v5.10 yocto kernel, I gave up using mainline DP driver and
reverted DP/psgtr/dpdma mainline
drivers to use SDK drivers instead.
If the DP driver can work in the near future, I would like switch to
mainline DP/psgtr/dpdma driver.
Xilinx is going to prepare v5.10 rebase tree with fixing these problems.
Is there any developing version based on v5.10 at Xilinx now? Wish for
some reference.
Thanks,
Quanyang
It should be available in Q1/2021.
Thanks,
Michal
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index 9868ca15dfc5..50d027d20239 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -43,6 +43,34 @@
#clock-cells = <0>;
clock-frequency = <27000000>;
};
+
+ dp_aclk: dp_aclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-accuracy = <100>;
+ };
+
+};
+
+&zynqmp_firmware {
+ zynqmp_clk: clock-controller {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,zynqmp-clk";
+ clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
+ <&aux_ref_clk>, <>_crx_ref_clk>;
+ clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
+ "aux_ref_clk", "gt_crx_ref_clk";
+ };
+};
+
+&xlnx_dpdma {
+ clocks = <&zynqmp_clk DPDMA_REF>;
+};
+
+&psgtr {
+ clocks = <&video_clk>, <&video_clk>, <&video_clk>, <&video_clk>;
};
&can0 {
@@ -220,3 +248,7 @@
&watchdog0 {
clocks = <&zynqmp_clk WDT>;
};
+
+&zynqmp_dpsub {
+ clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index 4f801721564f..7f0f5a698fe2 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU102 RevA";
@@ -138,6 +139,14 @@
status = "okay";
};
+&psgtr {
+ status = "okay";
+};
+
+&xlnx_dpdma {
+ status = "okay";
+};
+
&dcc {
status = "okay";
};
@@ -619,6 +628,12 @@
status = "okay";
};
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0";
+ phys = <&lane1 1 PHY_TYPE_DP 0 3>;
+};
+
&uart1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 3ec99f13c259..fe88a22baeb8 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -146,6 +146,11 @@
"gt_crx_ref_clk";
};
+ zynqmp_reset: reset-controller {
+ compatible = "xlnx,zynqmp-reset";
+ #reset-cells = <1>;
+ };
+
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
@@ -566,6 +571,21 @@
<0x0 0xfd3d0000 0x0 0x1000>;
reg-names = "serdes", "siou";
#phy-cells = <4>;
+
+ clock-names = "ref0", "ref1", "ref2", "ref3";
+
+ lane0: lane0 {
+ #phy-cells = <4>;
+ };
+ lane1: lane1 {
+ #phy-cells = <4>;
+ };
+ lane2: lane2 {
+ #phy-cells = <4>;
+ };
+ lane3: lane3 {
+ #phy-cells = <4>;
+ };
};
rtc: rtc@ffa60000 {
@@ -736,5 +756,89 @@
reg = <0x0 0xfd4d0000 0x0 0x1000>;
timeout-sec = <10>;
};
+
+ xlnx_dpdma: dma@fd4c0000 {
+ compatible = "xlnx,zynqmp-dpdma";
+ status = "disabled";
+ reg = <0x0 0xfd4c0000 0x0 0x1000>;
+ interrupts = <0 122 4>;
+ interrupt-parent = <&gic>;
+ clock-names = "axi_clk";
+ power-domains = <&zynqmp_firmware PD_DP>;
+ dma-channels = <6>;
+ #dma-cells = <1>;
+ dma-video0channel {
+ compatible = "xlnx,video0";
+ };
+ dma-video1channel {
+ compatible = "xlnx,video1";
+ };
+ dma-video2channel {
+ compatible = "xlnx,video2";
+ };
+ dma-graphicschannel {
+ compatible = "xlnx,graphics";
+ };
+ dma-audio0channel {
+ compatible = "xlnx,audio0";
+ };
+ dma-audio1channel {
+ compatible = "xlnx,audio1";
+ };
+ };
+
+ zynqmp_dpsub: zynqmp-display@fd4a0000 {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ status = "okay";
+ reg = <0x0 0xfd4a0000 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <&gic>;
+
+ resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
+ reset-names = "dp_rst";
+
+ clock-names = "dp_apb_clk", "dp_aud_clk",
+ "dp_vtc_pixel_clk_in";
+
+ power-domains = <&zynqmp_firmware PD_DP>;
+
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <&xlnx_dpdma 0>,
+ <&xlnx_dpdma 1>,
+ <&xlnx_dpdma 2>,
+ <&xlnx_dpdma 3>;
+
+ /* dummy node to indicate there's no child i2c device */
+ i2c-bus {
+ };
+
+ zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
+ compatible = "xlnx,dp-snd-codec";
+ clock-names = "aud_clk";
+ };
+
+ zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
+ compatible = "xlnx,dp-snd-pcm";
+ dmas = <&xlnx_dpdma 4>;
+ dma-names = "tx";
+ };
+
+ zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
+ compatible = "xlnx,dp-snd-pcm";
+ dmas = <&xlnx_dpdma 5>;
+ dma-names = "tx";
+ };
+
+ zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
+ compatible = "xlnx,dp-snd-card";
+ xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
+ <&zynqmp_dp_snd_pcm1>;
+ xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;
+ };
+ };
};
};
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
index 26328c76305b..0e34609b4b5a 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
@@ -96,7 +96,7 @@ static struct drm_driver zynqmp_dpsub_drm_driver = {
.fops = &zynqmp_dpsub_drm_fops,
- .name = "zynqmp-dpsub",
+ .name = "xlnx",
.desc = "Xilinx DisplayPort Subsystem Driver",
.date = "20130509",
.major = 1,
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