This issue is introduced by sdk commit 2345bf39fa33("HSD#1509827762:
arm64: dts: stratix10: add Intel FPGA Quad Speed Ethernet for Stratix10").
The qse feature is included latest Intel standard PFGA design by default, so
above commit add qse related dts node, and is included in dts files. But for
other FPGA designs(PCIe, GPIO and SGMII), the recorresponding dts files
don't need the qse feature, so add a condition to control whether include
the qse dtsi file or not.
Signed-off-by: Meng Li <meng...@windriver.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_ghrd.dts | 1 +
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_pcie.dts | 1 +
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_sgmii.dts | 1 +
4 files changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index c3624e455d21..6af2ebafbc35 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -4,7 +4,9 @@
*/
#include "socfpga_stratix10.dtsi"
+#ifndef DISABLE_QSE
#include "socfpga_stratix10_qse.dtsi"
+#endif
/ {
model = "SoCFPGA Stratix 10 SoCDK";
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_ghrd.dts
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_ghrd.dts
index a05fd640b2e5..ccacd54e536c 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_ghrd.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_ghrd.dts
@@ -3,6 +3,7 @@
* Copyright Altera Corporation (C) 2021. All rights reserved.
*/
+#define DISABLE_QSE
#include "socfpga_stratix10_socdk.dts"
/{
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_pcie.dts
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_pcie.dts
index 9b9f9d730142..37a5c6c1c74b 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_pcie.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_pcie.dts
@@ -3,6 +3,7 @@
* Copyright Altera Corporation (C) 2019. All rights reserved.
*/
+#define DISABLE_QSE
#include "socfpga_stratix10_socdk.dts"
/ {
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_sgmii.dts
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_sgmii.dts
index 76395decd44d..725bfceb3535 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_sgmii.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_sgmii.dts
@@ -3,6 +3,7 @@
* Copyright Altera Corporation (C) 2021. All rights reserved.
*/
+#define DISABLE_QSE
#include "socfpga_stratix10_socdk.dts"
/{
--
2.17.1
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