I was looking for a v3 that was completely plain text, so we could debug how you are sending these email that is corrupting the format.
Are you using git-send email or something else ? Bruce On Thu, Nov 16, 2023 at 12:54 PM Kadambathur Subramaniyam, Saravanan <saravanan.kadambathursubramani...@windriver.com> wrote: > > Hi Bruce, > > Could you please help to merge these patches?. > > Thanks > Saravanan > ________________________________ > From: linux-yocto@lists.yoctoproject.org <linux-yocto@lists.yoctoproject.org> > on behalf of Kadambathur Subramaniyam, Saravanan via lists.yoctoproject.org > <saravanan.kadambathursubramaniyam=windriver....@lists.yoctoproject.org> > Sent: Friday, November 10, 2023 7:45 PM > To: Bruce Ashfield <bruce.ashfi...@gmail.com> > Cc: linux-yocto@lists.yoctoproject.org <linux-yocto@lists.yoctoproject.org> > Subject: Re: [linux-yocto] [V2-revised] Microchip polarfire SoC - > yocto-kernel-cache & linux-yocto V2 patch. > > Hi Bruce, > This pull (v2) is to enable support for board Microchip Polarfire SoC ICICLE > kit. > Both standard and rt kernel are well tested against 6.1, these images boots > well and no error observed. > > Request you to create two branches in linux-yocto as below, and merge those > kernel patches to them? > v6.1/standard/microchip-polarfire-soc/ > v6.1/standard/preempt-rt/microchip-polarfire-soc/ > > Please note this pull request patches apply to both standard and rt cleanly > and hence sending one single pull request. Request you to merge these patches > in the above mentioned standard and rt kernel branches. > > V2 Changes: > > Removed mpfs_defconfig file from linux-yocto and created it in > yocto-kernel-cache > In the commit message, corrected microchip reference branch name as mchp+fpga > Fixed author name issue in 3 commits > Fixed typo in one of the commit. > Corrected overwriting of original commit "0a1b80ff4f72" > > ------------------------------------------------------------------------------------------------------------------------------------------------- > > The following changes since commit 780d811bb97bf34f2be6cab28d5a8b099154c40d: > > Merge tag 'v6.1.60' into v6.1/standard/base (2023-10-27 15:46:14 -0400) > > are available in the Git repository at: > > g...@github.com:SaravananWR/v6.1-std-base.git v2-microchip-polarfire-soc > > for you to fetch changes up to cb4611a3861cda4f3a8d7954f96ea8e0eb7265f5: > > riscv: dts: microchip: add the pac1934 to the icicle kit (2023-11-08 > 08:32:44 +0000) > > ---------------------------------------------------------------- > Andrew Jones (4): > riscv: Don't duplicate __ALTERNATIVE_CFG in __ALTERNATIVE_CFG_2 > riscv: alternatives: Don't name unused macro parameters > riscv: alternatives: Drop the underscores from the assembly macro names > riscv: Don't duplicate _ALTERNATIVE_CFG* macros > > Atish Patra (2): > of: Move of_dma_get_range to of_address.h > dma-mapping: Enable global non-coherent pool support for RISC-V > > laudiu Beznea (2): > net: macb: fix ethernet after resume > net: phylink: add helper to initialize phylink's phydev > > Conor Dooley (50): > soc: microchip: add generic service driver > soc: microchip: generic-service: warn if used > spi: microchip-core-qspi: add mpfs-qspi compatible > dt-bindings: dma: document the microchip fpga soft dma controller > pwm: add microchip soft ip corePWM driver > mailbox: mpfs: fix an incorrect mask width > mailbox: mpfs: ditch a useless busy check > mailbox: mpfs: check the service status in .tx_done() > fpga: add PolarFire SoC Auto Update support > soc: microchip: mpfs: fix some horrible alignment > soc: microchip: mpfs: use a consistent completion timeout > soc: microchip: mpfs: simplify error handling in > mpfs_blocking_transaction() > soc: microchip: mpfs: handle timeouts and failed services differently > soc: microchip: mpfs: add a prefix to rx_callback() > dt-bindings: soc: microchip: add a property for system controller flash > soc: microchip: mpfs: enable access to the system controller's flash > soc: microchip: mpfs: add auto-update subdev to system controller > dt-bindings: dma: sf-pdma: fix formatting issues > soc: sifive: select RISCV_DMA_NONCOHERENT > dt-bindings: usb: musb: microchip,mpfs-musb: allow dma-noncoherent > dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent > dt-bindings: mmc: cdns,sdhci: allow dma-noncoherent > soc: sifive: use an arch, not device initcall > riscv: dts: microchip: mask off some mmode interrupts > riscv: dts: microchip: add ccc clock controller to mpfs > riscv: dts: microchip: add specific compatible for mpfs' pdma > riscv: dts: microchip: add a missing space to the mpfs musb entry > riscv: dts: microchip: fix the mpfs' mailbox regs > riscv: dts: microchip: add the icicle's system controller qspi > riscv: dts: microchip: update the icicle's fabric content > riscv: dts: microchip: add top level address/size cells to icicle > riscv: dts: microchip: add overlaid memory to icicle kit > riscv: dts: microchip: switch the icicle's usb to otg mode > riscv: dts: microchip: add a dts for amp on icicle kit > riscv: dts: microchip: add a tysom dts > riscv: dts: microchip: annotate icicle peripherals with dma-noncoherent > dt-bindings: net: cdns,macb: allow dma-noncoherent > RISC-V: set memblock allocation direction to bottom-up > riscv: dts: microchip: add mpfs specific macb reset support > riscv: dts: microchip: add the sevkit's system controller spi flash > fpga: auto-update: refuse auto-update if no golden image > riscv: dts: microchip: fix system controller qspi clock parentage > fpga: auto-update: rename user-visible uses of upgrade to update > pwm: microchip-core: fix build after stable merge > fpga: auto-update: prevent conflicting prints > uio: add microchip uio can driver > uio: add microchip uio fpga dma driver > iio: adc: update pac193x driver to v0.0.2 > iio: adc: get the pac193x revision id correctly > iio: adc: pac193x: fixup compilation issues with v6.1 > > Daire McNamara (13): > usb: musb: mpfs: pass dma_range_map to musb from mpfs > PCI: microchip: Remove cast warning for devm_add_action_or_reset() arg > PCI: microchip: Align register, offset, and mask names with hw docs > PCI: microchip: Enable event handlers to access bridge and ctrl ptrs > PCI: microchip: Clean up initialisation of interrupts > PCI: microchip: Gather MSI information from hardware config registers > PCI: microchip: Re-partition code between probe() and init() > PCI: microchip: Partition outbound address translation > PCI: microchip: Partition inbound address translation > soc: sifive: l2cache: enable adding SiFive L2 controller driver to MPFS > soc: sifive: ccache: add cache flushing operations > net: macb: Shorten max_tx_len to 4KiB - 56 on mpfs > dma: allow dma_reserved_default_memory to be updated > > Durai Manickam KR (2): > net: macb: Add PTP support to EMAC > net: macb: Add PTP support to GEM > > Geert Uytterhoeven (1): > gpio: mpfs: Make the irqchip immutable > > Guillaume Socquet (1): > mtd: spi-nor: sst: Unlock addition for sst26vf016 > > Heiko Stuebner (13): > RISC-V: fix funct4 definition for c.jalr in parse_asm.h > RISC-V: add prefix to all constants/macros in parse_asm.h > RISC-V: detach funct-values from their offset > RISC-V: add ebreak instructions to definitions > RISC-V: add auipc elements to parse_asm header > RISC-V: Move riscv_insn_is_* macros into a common header > RISC-V: rename parse_asm.h to insn.h > RISC-V: kprobes: use central defined funct3 constants > RISC-V: add U-type imm parsing to insn.h header > RISC-V: add rd reg parsing to insn.h header > RISC-V: add helpers for handling immediates in U-type and I-type pairs > RISC-V: fix compile error from deduplicated __ALTERNATIVE_CFG_2 > RISC-V: fix auipc-jalr addresses in patched alternatives > > Horatiu Vultur (4): > net: micrel: Add support for lan8841 PHY > net: micrel: Cable Diagnostics feature for lan8841 PHY > net: micrel: Add PHC support for lan8841 > net: phy: micrel: Add support for PTP_PF_PEROUT for lan8841 > > Jamie Gibbons (2): > riscv: dts: microchip: mpfs: update gpio interrupt cells > dt-bindings: gpio: update microchip int cells > > Lad Prabhakar (1): > riscv: mm: dma-noncoherent: Switch using function pointers for cache > management > > Lewis Hanly (2): > gpio: mpfs: add polarfire soc gpio support > iio: adc: add microchip pac193x driver > > Nicolas Ferre (1): > net: macb: add support for gmac to sam9x7 > > Robert Hancock (1): > net: macb: simplify TX timestamp handling > > Roman Gushchin (1): > net: macb: implement live mac addr change > > Shravan Chippa (4): > dt-bindings: dma: sf-pdma: add new compatible name > dma: sf-pdma: add mpfs-pdma compatible name > dt-bindings: misc: microchip,mpfs-dma-proxy > misc: add mchp dma proxy driver > > Tudor Ambarus (8): > mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag > mtd: spi-nor: macronix: Add support for mx66lm1g45g > spi: spi-mem: Allow specifying the byte order in DTR mode > mtd: spi-nor: core: Allow specifying the byte order in DTR mode > mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT > mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag > mtd: spi-nor: macronix: Set SPI_NOR_DTR_BSWAP16 on mx66lm1g45g > mtd: spi-nor: macronix: Fix readid protocol at octal dtr disable > > Valentina Fernandez (7): > dt-bindings: include: mailbox: add defines for miv-ihc > dt-bindings: mailbox: add binding for miv-ihc > mbox: add mi-v ihc support > dt-bindings: PCI: microchip: update number of items in ranges property > dt-bindings: remoteproc: add binding for miv-remoteproc > remoteproc: add support for Microchip Mi-V remoteproc platform driver > riscv: dts: microchip: add the pac1934 to the icicle kit > > Vattipalli Praveen (1): > dt-bindings: riscv: microchip: add mpfs video kit > > shravan kumar (1): > dmaengine: sf-pdma: Support of_dma_controller_register() > > Documentation/devicetree/bindings/dma/microchip,mpfs-fpga-dma.yaml > | 49 ++ > Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > | 12 +- > Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml > | 2 +- > Documentation/devicetree/bindings/mailbox/microchip,miv-ihc.yaml > | 59 ++ > Documentation/devicetree/bindings/misc/microchip,mpfs-dma-proxy.yaml > | 45 ++ > Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml > | 2 + > Documentation/devicetree/bindings/net/cdns,macb.yaml > | 2 + > Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > | 5 +- > Documentation/devicetree/bindings/remoteproc/microchip,miv-remoteproc.yaml > | 72 ++ > Documentation/devicetree/bindings/riscv/microchip.yaml > | 1 + > > Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml > | 10 + > Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml > | 2 + > arch/riscv/Kconfig > | 1 + > arch/riscv/boot/dts/microchip/Makefile > | 2 + > arch/riscv/boot/dts/microchip/mpfs-icicle-kit-context-a.dts > | 379 +++++++++ > arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi > | 166 ++-- > arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts > | 179 ++++- > arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts > | 14 + > arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi > | 18 + > arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts > | 165 ++++ > arch/riscv/boot/dts/microchip/mpfs.dtsi > | 82 +- > arch/riscv/errata/thead/errata.c > | 70 ++ > arch/riscv/include/asm/alternative-macros.h > | 99 +-- > arch/riscv/include/asm/alternative.h > | 3 + > arch/riscv/include/asm/dma-noncoherent.h > | 74 ++ > arch/riscv/include/asm/errata_list.h > | 53 -- > arch/riscv/include/asm/insn.h > | 345 ++++++++ > arch/riscv/include/asm/parse_asm.h > | 224 ------ > arch/riscv/kernel/alternative.c > | 56 ++ > arch/riscv/kernel/cpufeature.c > | 4 + > arch/riscv/kernel/kgdb.c > | 63 +- > arch/riscv/kernel/probes/simulate-insn.c > | 19 +- > arch/riscv/kernel/probes/simulate-insn.h > | 26 +- > arch/riscv/mm/dma-noncoherent.c > | 70 +- > arch/riscv/mm/init.c > | 1 + > drivers/dma/sf-pdma/sf-pdma.c > | 68 +- > drivers/dma/sf-pdma/sf-pdma.h > | 6 + > drivers/fpga/Kconfig > | 9 + > drivers/fpga/Makefile > | 1 + > drivers/fpga/microchip-auto-update.c > | 502 ++++++++++++ > drivers/gpio/Kconfig > | 7 + > drivers/gpio/Makefile > | 1 + > drivers/gpio/gpio-mpfs.c > | 320 ++++++++ > drivers/iio/adc/Kconfig > | 12 + > drivers/iio/adc/Makefile > | 1 + > drivers/iio/adc/pac193x.c > | 1688 +++++++++++++++++++++++++++++++++++++++ > drivers/mailbox/Kconfig > | 13 + > drivers/mailbox/Makefile > | 2 + > drivers/mailbox/mailbox-miv-ihc.c > | 233 ++++++ > drivers/mailbox/mailbox-mpfs.c > | 45 +- > drivers/misc/Kconfig > | 8 + > drivers/misc/Makefile > | 1 + > drivers/misc/mpfs-dma-proxy.c > | 417 ++++++++++ > drivers/mtd/spi-nor/core.c > | 37 +- > drivers/mtd/spi-nor/core.h > | 9 +- > drivers/mtd/spi-nor/macronix.c > | 132 +++ > drivers/mtd/spi-nor/sfdp.c > | 3 + > drivers/mtd/spi-nor/sfdp.h > | 1 + > drivers/mtd/spi-nor/sst.c > | 4 +- > drivers/net/ethernet/cadence/macb.h > | 30 +- > drivers/net/ethernet/cadence/macb_main.c > | 55 +- > drivers/net/ethernet/cadence/macb_ptp.c > | 83 +- > drivers/net/phy/micrel.c > | 1618 +++++++++++++++++++++++++++++++------ > drivers/net/phy/phylink.c > | 10 + > drivers/of/of_private.h > | 8 - > drivers/pci/controller/pcie-microchip-host.c > | 680 +++++++++++----- > drivers/pwm/Kconfig > | 10 + > drivers/pwm/Makefile > | 1 + > drivers/pwm/pwm-microchip-core.c > | 441 ++++++++++ > drivers/remoteproc/Kconfig > | 14 + > drivers/remoteproc/Makefile > | 1 + > drivers/remoteproc/miv_remoteproc.c > | 509 ++++++++++++ > drivers/soc/Makefile > | 2 +- > drivers/soc/microchip/Kconfig > | 17 + > drivers/soc/microchip/Makefile > | 1 + > drivers/soc/microchip/mpfs-generic-service.c > | 211 +++++ > drivers/soc/microchip/mpfs-sys-controller.c > | 85 +- > drivers/soc/sifive/Kconfig > | 3 +- > drivers/soc/sifive/sifive_ccache.c > | 37 +- > drivers/spi/spi-microchip-core-qspi.c > | 1 + > drivers/uio/Kconfig > | 14 + > drivers/uio/Makefile > | 2 + > drivers/uio/uio-microchip-can.c > | 203 +++++ > drivers/uio/uio-microchip-dma.c > | 167 ++++ > drivers/usb/musb/mpfs.c > | 2 +- > include/dt-bindings/mailbox/miv-ihc.h > | 17 + > include/linux/mailbox/miv_ihc.h > | 39 + > include/linux/micrel_phy.h > | 1 + > include/linux/mtd/spi-nor.h > | 17 + > include/linux/of_address.h > | 12 + > include/linux/phylink.h > | 1 + > include/linux/spi/spi-mem.h > | 3 + > include/soc/microchip/mpfs.h > | 2 + > include/uapi/misc/mpfs-dma-proxy.h > | 42 + > kernel/dma/coherent.c > | 52 +- > 95 files changed, 9173 insertions(+), 1112 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/dma/microchip,mpfs-fpga-dma.yaml > create mode 100644 > Documentation/devicetree/bindings/mailbox/microchip,miv-ihc.yaml > create mode 100644 > Documentation/devicetree/bindings/misc/microchip,mpfs-dma-proxy.yaml > create mode 100644 > Documentation/devicetree/bindings/remoteproc/microchip,miv-remoteproc.yaml > create mode 100644 > arch/riscv/boot/dts/microchip/mpfs-icicle-kit-context-a.dts > create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi > create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts > create mode 100644 arch/riscv/include/asm/dma-noncoherent.h > create mode 100644 arch/riscv/include/asm/insn.h > delete mode 100644 arch/riscv/include/asm/parse_asm.h > create mode 100644 drivers/fpga/microchip-auto-update.c > create mode 100644 drivers/gpio/gpio-mpfs.c > create mode 100644 drivers/iio/adc/pac193x.c > create mode 100644 drivers/mailbox/mailbox-miv-ihc.c > create mode 100644 drivers/misc/mpfs-dma-proxy.c > create mode 100644 drivers/pwm/pwm-microchip-core.c > create mode 100644 drivers/remoteproc/miv_remoteproc.c > create mode 100644 drivers/soc/microchip/mpfs-generic-service.c > create mode 100644 drivers/uio/uio-microchip-can.c > create mode 100644 drivers/uio/uio-microchip-dma.c > create mode 100644 include/dt-bindings/mailbox/miv-ihc.h > create mode 100644 include/linux/mailbox/miv_ihc.h > create mode 100644 include/uapi/misc/mpfs-dma-proxy.h > ------------------------------------------------------------------------------------------------------------------------------------------------- > Consolidate commit log : > cb4611a3861c (HEAD -> v2-microchip-polarfire-soc, > origin/v2-microchip-polarfire-soc) riscv: dts: microchip: add the pac1934 to > the icicle kit > 8cb7683f841a iio: adc: pac193x: fixup compilation issues with v6.1 > 1a52910bc16c iio: adc: get the pac193x revision id correctly > d2db52a56ed3 iio: adc: update pac193x driver to v0.0.2 > 109467ae50e6 iio: adc: add microchip pac193x driver > 7d8c9345317e uio: add microchip uio fpga dma driver > 00ea049c3a7c uio: add microchip uio can driver > 7e8f467bde3f net: phylink: add helper to initialize phylink's phydev > cf4fa30d3b60 fpga: auto-update: prevent conflicting prints > 7490e589527b pwm: microchip-core: fix build after stable merge > 08a655fac3e2 fpga: auto-update: rename user-visible uses of upgrade to update > 599ecc5d258d riscv: dts: microchip: fix system controller qspi clock parentage > 2659a080e83f dt-bindings: riscv: microchip: add mpfs video kit > 99e9f45bb334 dt-bindings: gpio: update microchip int cells > 187b3715d62b riscv: dts: microchip: mpfs: update gpio interrupt cells > ad1400313a8f fpga: auto-update: refuse auto-update if no golden image > 66671d849aaf riscv: dts: microchip: add the sevkit's system controller spi > flash > 84b4acb3ffda riscv: dts: microchip: add mpfs specific macb reset support > 57b59dc27d41 mtd: spi-nor: sst: Unlock addition for sst26vf016 > a5aae95b54d5 mtd: spi-nor: macronix: Fix readid protocol at octal dtr disable > 12a6e5276892 mtd: spi-nor: macronix: Set SPI_NOR_DTR_BSWAP16 on mx66lm1g45g > e838e46fb5d4 mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag > 4fdf9025a89e mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT > a02bc405fe58 mtd: spi-nor: core: Allow specifying the byte order in DTR mode > 54f4e97f93a8 RISC-V: fix auipc-jalr addresses in patched alternatives > 1077c524e463 spi: spi-mem: Allow specifying the byte order in DTR mode > 3e1c4630db67 RISC-V: set memblock allocation direction to bottom-up > ff2cac386265 dma-mapping: Enable global non-coherent pool support for RISC-V > 63c594ff0ca1 dma: allow dma_reserved_default_memory to be updated > 39e7472a2faf of: Move of_dma_get_range to of_address.h > 415cd33444a4 riscv: mm: dma-noncoherent: Switch using function pointers for > cache management > 7fe2457ec8a9 RISC-V: fix compile error from deduplicated __ALTERNATIVE_CFG_2 > d6bf3ebd2b5c riscv: Don't duplicate _ALTERNATIVE_CFG* macros > 9ba45c342a2d riscv: alternatives: Drop the underscores from the assembly > macro names > d5511b5b378c riscv: alternatives: Don't name unused macro parameters > 2ef0ec0bde5d riscv: Don't duplicate __ALTERNATIVE_CFG in __ALTERNATIVE_CFG_2 > a71042c82b1e RISC-V: add helpers for handling immediates in U-type and I-type > pairs > 56102c995850 RISC-V: add rd reg parsing to insn.h header > d400adf674dc RISC-V: add U-type imm parsing to insn.h header > ed6c8f319f4a RISC-V: kprobes: use central defined funct3 constants > 9e5fc44e80f9 RISC-V: rename parse_asm.h to insn.h > c865f7d1876c RISC-V: Move riscv_insn_is_* macros into a common header > b3224e1b823a RISC-V: add auipc elements to parse_asm header > a6e43784161b RISC-V: add ebreak instructions to definitions > a6fc264f4330 RISC-V: detach funct-values from their offset > 259d0d96c56d RISC-V: add prefix to all constants/macros in parse_asm.h > 7452338249fd RISC-V: fix funct4 definition for c.jalr in parse_asm.h > ae6f1358b077 net: phy: micrel: Add support for PTP_PF_PEROUT for lan8841 > 00e5917a350a net: micrel: Add PHC support for lan8841 > f292eb906864 net: micrel: Cable Diagnostics feature for lan8841 PHY > c51715563fb1 net: micrel: Add support for lan8841 PHY > c5ed6af7ca27 net: macb: Shorten max_tx_len to 4KiB - 56 on mpfs > 9dc9c5c95982 dt-bindings: net: cdns,macb: allow dma-noncoherent > 1342f4e68162 riscv: dts: microchip: annotate icicle peripherals with > dma-noncoherent > 785d8ffe77f4 riscv: dts: microchip: add a tysom dts > 91e98cce1fe7 riscv: dts: microchip: add a dts for amp on icicle kit > ba63fc1d045c riscv: dts: microchip: switch the icicle's usb to otg mode > d735d4bc1fdc riscv: dts: microchip: add overlaid memory to icicle kit > 8af0037f867a riscv: dts: microchip: add top level address/size cells to icicle > e757528bf25e riscv: dts: microchip: update the icicle's fabric content > c83764d4ee09 riscv: dts: microchip: add the icicle's system controller qspi > 48b484700dc4 riscv: dts: microchip: fix the mpfs' mailbox regs > a7dfa5c68457 riscv: dts: microchip: add a missing space to the mpfs musb entry > 86cce74e4609 riscv: dts: microchip: add specific compatible for mpfs' pdma > 708b11075cbf riscv: dts: microchip: add ccc clock controller to mpfs > a91b2ffc97d0 riscv: dts: microchip: mask off some mmode interrupts > e3c1565cce71 soc: sifive: use an arch, not device initcall > 5344bdfc977d dt-bindings: mmc: cdns,sdhci: allow dma-noncoherent > ed22acff6dad dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent > 511a4de70889 dt-bindings: usb: musb: microchip,mpfs-musb: allow > dma-noncoherent > 69787b4b2601 soc: sifive: select RISCV_DMA_NONCOHERENT > 668274ac00c1 dt-bindings: dma: sf-pdma: fix formatting issues > 30f21f83d4b7 soc: microchip: mpfs: add auto-update subdev to system controller > f9febd8b78d8 soc: microchip: mpfs: enable access to the system controller's > flash > 76ee66dd097f dt-bindings: soc: microchip: add a property for system > controller flash > 0a28d2056b73 soc: microchip: mpfs: add a prefix to rx_callback() > 7a22e651b930 soc: microchip: mpfs: handle timeouts and failed services > differently > 86ac34ba4fef soc: microchip: mpfs: simplify error handling in > mpfs_blocking_transaction() > 234500ac58eb soc: microchip: mpfs: use a consistent completion timeout > 68ad2b269fd3 soc: microchip: mpfs: fix some horrible alignment > ab5ae5895b36 soc: sifive: ccache: add cache flushing operations > f3b34c8a8128 fpga: add PolarFire SoC Auto Update support > 6966041ed033 mailbox: mpfs: check the service status in .tx_done() > 2ba819d2418c mailbox: mpfs: ditch a useless busy check > 959656c4b132 misc: add mchp dma proxy driver > a4736f1a234c mailbox: mpfs: fix an incorrect mask width > 6c188551c893 remoteproc: add support for Microchip Mi-V remoteproc platform > driver > 6d89a10f8417 dt-bindings: remoteproc: add binding for miv-remoteproc > dd20ad0b33da soc: sifive: l2cache: enable adding SiFive L2 controller driver > to MPFS > c373f6a65eaf mtd: spi-nor: macronix: Add support for mx66lm1g45g > 0b366ce7f040 mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info > fixup_flag > 855e8655d85b PCI: microchip: Partition inbound address translation > 0c4cd58ac5dd PCI: microchip: Partition outbound address translation > 9e9e372bc7b7 PCI: microchip: Re-partition code between probe() and init() > 3894349bca66 PCI: microchip: Gather MSI information from hardware config > registers > 5ce5a21190da PCI: microchip: Clean up initialisation of interrupts > c73151fee77a PCI: microchip: Enable event handlers to access bridge and ctrl > ptrs > e624e7d69171 PCI: microchip: Align register, offset, and mask names with hw > docs > ce01a6208447 PCI: microchip: Remove cast warning for > devm_add_action_or_reset() arg > ea86dab4e6da dt-bindings: PCI: microchip: update number of items in ranges > property > 471c2f1366cb usb: musb: mpfs: pass dma_range_map to musb from mpfs > 543cbf1e7cae gpio: mpfs: Make the irqchip immutable > 0e461f7dcc81 gpio: mpfs: add polarfire soc gpio support > 7d11021f8ae0 pwm: add microchip soft ip corePWM driver > f9d913cbd983 net: macb: Add PTP support to GEM > b043705c6d54 net: macb: Add PTP support to EMAC > fb983353a31e net: macb: simplify TX timestamp handling > fbf87f3e72ba net: macb: fix ethernet after resume > abef50cf878b dt-bindings: misc: microchip,mpfs-dma-proxy > 5630b160ac39 dma: sf-pdma: add mpfs-pdma compatible name > 7482e4157ab9 dt-bindings: dma: sf-pdma: add new compatible name > ad8391f30a9b dmaengine: sf-pdma: Support of_dma_controller_register() > da19072af764 dt-bindings: dma: document the microchip fpga soft dma controller > 197fc5c3a9e6 spi: microchip-core-qspi: add mpfs-qspi compatible > d76c16d68a18 mbox: add mi-v ihc support > 637090b40eb5 dt-bindings: mailbox: add binding for miv-ihc > a8a6e5019099 dt-bindings: include: mailbox: add defines for miv-ihc > 76f43741e9c3 net: macb: add support for gmac to sam9x7 > bc9cc1e89de8 soc: microchip: generic-service: warn if used > 8ed963be7df1 soc: microchip: add generic service driver > bbd843498564 net: macb: implement live mac addr change > ------------------------------------------------------------------------------------------------------------------------------------------------- > Thanks > Saravanan > > ________________________________ > From: Kadambathur Subramaniyam, Saravanan > <saravanan.kadambathursubramani...@windriver.com> > Sent: Friday, November 10, 2023 7:31 PM > To: Bruce Ashfield <bruce.ashfi...@gmail.com> > Cc: linux-yocto@lists.yoctoproject.org <linux-yocto@lists.yoctoproject.org> > Subject: Re: [V2-revised] Microchip polarfire SoC - yocto-kernel-cache & > linux-yocto V2 patch. > > Hi Bruce, > Please find below the yocto-kernel-cache patch. > Request you to merge this patch in yocto-kernel-cache yocto-6.1 branch. > ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ > V2 Change log: > Following changes done in the yocto-kernel-cache BSP config file: > Removed: > CONFIG_NO_HZ_IDLE=y > CONFIG_HIGH_RES_TIMERS=y > CONFIG_CFS_BANDWIDTH=y > CONFIG_BLK_DEV_INITRD=y > CONFIG_EXPERT=y > CONFIG_JUMP_LABEL=y > CONFIG_MODULES=y > CONFIG_MODULE_UNLOAD=y > CONFIG_NET=y > CONFIG_PACKET=y > CONFIG_INET=y > CONFIG_DEVTMPFS=y > CONFIG_DEVTMPFS_MOUNT=y > CONFIG_BLK_DEV_LOOP=y > CONFIG_USB_STORAGE=m > CONFIG_SPARSEMEM_MANUAL=y > CONFIG_EXT4_FS=y > CONFIG_EXT4_FS_POSIX_ACL=y > CONFIG_FANOTIFY=y > CONFIG_TMPFS=y > CONFIG_TMPFS_POSIX_ACL=y > CONFIG_PRINTK_TIME=y > CONFIG_DEBUG_FS=y > CONFIG_SCHED_STACK_END_CHECK=y > CONFIG_SOFTLOCKUP_DETECTOR=y > CONFIG_WQ_WATCHDOG=y > CONFIG_STACKTRACE=y > CONFIG_STRICT_DEVMEM=y > CONFIG_CMDLINE_BOOL=y > CONFIG_CMDLINE="earlycon=sbi root=/dev/mmcblk0p3 rootwait > uio_pdrv_genirq.of_id=generic-uio" > CONFIG_INPUT_JOYDEV=m > CONFIG_INPUT_JOYSTICK=y > CONFIG_JOYSTICK_SENSEHAT=m > CONFIG_AUXDISPLAY=y > CONFIG_SENSEHAT_DISPLAY=m > CONFIG_HTS221=m > CONFIG_IIO_ST_PRESS=m > CONFIG_IIO_ST_LSM6DSX=m > CONFIG_IIO_ST_MAGN_3AXIS=m > CONFIG_IIO_ST_MAGN_SPI_3AXIS=n > CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n > CONFIG_MTD_UBI=y > CONFIG_MTD_CMDLINE_PARTS=y > CONFIG_UBIFS_FS=y > > Added: > CONFIG_NR_CPUS=4 > > Modifed to static: > CONFIG_SPI_SPIDEV=y > CONFIG_PMBUS=y > CONFIG_USB_ACM=y > CONFIG_USB_SERIAL=y > CONFIG_RPMSG_CHAR=y > CONFIG_RPMSG_CTRL=y > CONFIG_RPMSG_TTY=y > CONFIG_IIO=y > CONFIG_IIO_SW_DEVICE=y > CONFIG_IIO_SW_TRIGGER=y > CONFIG_PAC193X=y > ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ > > From 551ea4aa5214e270265dd23d1dd1b5844fe377fc Mon Sep 17 00:00:00 2001 > From: "Saravanan.K.S" <saravanan.kadambathursubramani...@windriver.com> > Date: Tue, 7 Nov 2023 10:46:02 +0000 > Subject: [PATCH] microchip-polarfire-soc: add configure file for > microchip-polarfire-soc BSP in kernel-cache > > Signed-off-by: Saravanan.K.S <saravanan.kadambathursubramani...@windriver.com> > --- > .../microchip-polarfire-soc-preempt-rt.scc | 8 ++ > .../microchip-polarfire-soc-standard.scc | 8 ++ > .../microchip-polarfire-soc.cfg | 106 ++++++++++++++++++ > .../microchip-polarfire-soc.scc | 5 + > 4 files changed, 127 insertions(+) > create mode 100755 > bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc > create mode 100755 > bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc > create mode 100644 bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg > create mode 100755 bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc > > diff --git > a/bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc > b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc > new file mode 100755 > index 00000000..ce1bc266 > --- /dev/null > +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-preempt-rt.scc > @@ -0,0 +1,8 @@ > +# SPDX-License-Identifier: MIT > +define KMACHINE microchip-polarfire-soc > +define KTYPE preempt-rt > +define KARCH riscv64 > + > +include ktypes/preempt-rt > + > +include microchip-polarfire-soc.scc > diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc > b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc > new file mode 100755 > index 00000000..21d69d5a > --- /dev/null > +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc-standard.scc > @@ -0,0 +1,8 @@ > +# SPDX-License-Identifier: MIT > +define KMACHINE microchip-polarfire-soc > +define KTYPE standard > +define KARCH riscv64 > + > +include ktypes/standard > + > +include microchip-polarfire-soc.scc > diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg > b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg > new file mode 100644 > index 00000000..ba02f3c0 > --- /dev/null > +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.cfg > @@ -0,0 +1,106 @@ > +# SPDX-License-Identifier: MIT > +.......................................................................... > +. WARNING > +. > +. This file is a kernel configuration fragment, and not a full kernel > +. configuration file. The final kernel configuration is made up of > +. an assembly of processed fragments, each of which is designed to > +. capture a specific part of the final configuration (e.g. platform > +. configuration, feature configuration, and board specific hardware > +. configuration). For more information on kernel configuration, please > +. consult the product documentation. > +. > +.......................................................................... > + > +# mpfs_defconfig > +CONFIG_SOC_MICROCHIP_POLARFIRE=y > +CONFIG_SMP=y > +CONFIG_NR_CPUS=4 > +CONFIG_PCI=y > +CONFIG_PCI_HOST_GENERIC=y > +CONFIG_PCIE_MICROCHIP_HOST=y > +CONFIG_FW_LOADER_USER_HELPER=y > +CONFIG_MTD=y > +CONFIG_MTD_SPI_NAND=y > +CONFIG_MTD_SPI_NOR=y > +CONFIG_OF_OVERLAY=y > +CONFIG_OF_CONFIGFS=y > +CONFIG_BLK_DEV_NVME=y > +CONFIG_BLK_DEV_SD=y > +CONFIG_ATA=y > +CONFIG_NETDEVICES=y > +CONFIG_MACB=y > +CONFIG_MICROSEMI_PHY=y > +CONFIG_MICREL_PHY=y > +CONFIG_SERIAL_8250=y > +CONFIG_SERIAL_8250_CONSOLE=y > +CONFIG_SERIAL_OF_PLATFORM=y > +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y > +CONFIG_HW_RANDOM=y > +CONFIG_HW_RANDOM_POLARFIRE_SOC=y > +CONFIG_I2C=y > +CONFIG_I2C_CHARDEV=y > +CONFIG_I2C_MICROCHIP_CORE=y > +CONFIG_SPI=y > +CONFIG_SPI_MICROCHIP_CORE=y > +CONFIG_SPI_MICROCHIP_CORE_QSPI=y > +CONFIG_SPI_SPIDEV=y > +CONFIG_GPIOLIB=y > +CONFIG_GPIO_SYSFS=y > +CONFIG_GPIO_POLARFIRE_SOC=y > +CONFIG_PMBUS=y > +CONFIG_POWER_RESET=y > +CONFIG_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_XHCI_PLATFORM=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_EHCI_HCD_PLATFORM=y > +CONFIG_USB_OHCI_HCD=y > +CONFIG_USB_OHCI_HCD_PLATFORM=y > +CONFIG_USB_ACM=y > +CONFIG_USB_MUSB_HDRC=y > +CONFIG_USB_MUSB_POLARFIRE_SOC=y > +CONFIG_USB_INVENTRA_DMA=y > +CONFIG_USB_SERIAL=y > +CONFIG_NOP_USB_XCEIV=y > +CONFIG_MMC=y > +CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_PLTFM=y > +CONFIG_MMC_SDHCI_CADENCE=y > +CONFIG_MMC_SPI=y > +CONFIG_RTC_CLASS=y > +CONFIG_RTC_DRV_POLARFIRE_SOC=y > +CONFIG_DMADEVICES=y > +CONFIG_SF_PDMA=y > +CONFIG_MPFS_DMA_PROXY=y > +CONFIG_UIO=y > +CONFIG_UIO_PDRV_GENIRQ=y > +CONFIG_UIO_DMEM_GENIRQ=y > +CONFIG_UIO_MICROCHIP_CAN=y > +CONFIG_UIO_MICROCHIP_DMA=y > +CONFIG_MAILBOX=y > +CONFIG_POLARFIRE_SOC_MAILBOX=y > +CONFIG_MIV_IHC=y > +CONFIG_REMOTEPROC=y > +CONFIG_REMOTEPROC_CDEV=y > +CONFIG_MIV_REMOTEPROC=y > +CONFIG_RPMSG_CHAR=y > +CONFIG_RPMSG_CTRL=y > +CONFIG_RPMSG_MIV=y > +CONFIG_RPMSG_TTY=y > +CONFIG_RPMSG_VIRTIO=y > +CONFIG_POLARFIRE_SOC_SYS_CTRL=y > +CONFIG_POLARFIRE_SOC_GENERIC_SERVICE=m > +CONFIG_SIFIVE_CCACHE=y > +CONFIG_IIO=y > +CONFIG_IIO_SW_DEVICE=y > +CONFIG_IIO_SW_TRIGGER=y > +CONFIG_PAC193X=y > +CONFIG_PWM=y > +CONFIG_PWM_MICROCHIP_CORE=y > +CONFIG_RESET_CONTROLLER=y > +CONFIG_FPGA=y > +CONFIG_FPGA_BRIDGE=y > +CONFIG_FPGA_REGION=y > +CONFIG_FPGA_MGR_MICROCHIP_AUTO_UPDATE=y > +CONFIG_FPGA_MGR_MICROCHIP_SPI=y > diff --git a/bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc > b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc > new file mode 100755 > index 00000000..3a8b9182 > --- /dev/null > +++ b/bsp/microchip-polarfire-soc/microchip-polarfire-soc.scc > @@ -0,0 +1,5 @@ > +# SPDX-License-Identifier: MIT > +kconf hardware microchip-polarfire-soc.cfg > + > +include cfg/usb-mass-storage.scc > +include cfg/fs/flash_fs.scc > -- > 2.40.0 > > Thanks > Saravanan > > > > ________________________________ > From: Kevin Hao > Sent: Friday, November 10, 2023 6:16 PM > To: Kadambathur Subramaniyam, Saravanan > Cc: Bruce Ashfield; linux-yocto@lists.yoctoproject.org; G Pillai, Hari > Subject: Re: [V2-revised] Microchip polarfire SoC - yocto-kernel-cache & > linux-yocto V2 patch. > > On Fri, Nov 10, 2023 at 12:21:49PM +0000, Kadambathur Subramaniyam, Saravanan > wrote: > > //Changed subject line > > Hi Bruce > > We closed all the internal review comments which Kexin mentioned in his > > below > > email. He approved the updated patch. > > Hi Saravanan, > > For the kernel cache change, since there is only one patch, you should sent > it as > standalone patch. It is more easy to comment than a pull request. Please also > remember to summarize the changes compare to the previous version. > > For the kernel patches, I suggest you resent the pull request. Please make > sure > to use plain text instead of HTML in your pull request. > > Thanks, > Kevin -- - Thou shalt not follow the NULL pointer, for chaos and madness await thee at its end - "Use the force Harry" - Gandalf, Star Trek II
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