This patch is to add v6.6 kernel cache support for nxp-s32g bsp. And the .scc and .cfg files are all based on v6.1 kernel cache's and SDK BSP41's kernel configures.
Signed-off-by: Zhantao Tang <zhantao.t...@windriver.com> --- bsp/nxp-s32g/nxp-s32g-preempt-rt.scc | 8 ++ bsp/nxp-s32g/nxp-s32g-standard.scc | 8 ++ bsp/nxp-s32g/nxp-s32g.cfg | 195 +++++++++++++++++++++++++++ bsp/nxp-s32g/nxp-s32g.scc | 7 + 4 files changed, 218 insertions(+) create mode 100755 bsp/nxp-s32g/nxp-s32g-preempt-rt.scc create mode 100755 bsp/nxp-s32g/nxp-s32g-standard.scc create mode 100644 bsp/nxp-s32g/nxp-s32g.cfg create mode 100755 bsp/nxp-s32g/nxp-s32g.scc diff --git a/bsp/nxp-s32g/nxp-s32g-preempt-rt.scc b/bsp/nxp-s32g/nxp-s32g-preempt-rt.scc new file mode 100755 index 00000000..8a3bad77 --- /dev/null +++ b/bsp/nxp-s32g/nxp-s32g-preempt-rt.scc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: MIT +define KMACHINE nxp-s32g +define KTYPE preempt-rt +define KARCH arm64 + +include ktypes/preempt-rt + +include nxp-s32g.scc diff --git a/bsp/nxp-s32g/nxp-s32g-standard.scc b/bsp/nxp-s32g/nxp-s32g-standard.scc new file mode 100755 index 00000000..0614ad55 --- /dev/null +++ b/bsp/nxp-s32g/nxp-s32g-standard.scc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: MIT +define KMACHINE nxp-s32g +define KTYPE standard +define KARCH arm64 + +include ktypes/standard + +include nxp-s32g.scc diff --git a/bsp/nxp-s32g/nxp-s32g.cfg b/bsp/nxp-s32g/nxp-s32g.cfg new file mode 100644 index 00000000..57ac3a18 --- /dev/null +++ b/bsp/nxp-s32g/nxp-s32g.cfg @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: MIT +.......................................................................... +. WARNING +. +. This file is a kernel configuration fragment, and not a full kernel +. configuration file. The final kernel configuration is made up of +. an assembly of processed fragments, each of which is designed to +. capture a specific part of the final configuration (e.g. platform +. configuration, feature configuration, and board specific hardware +. configuration). For more information on kernel configuration, please +. consult the product documentation. +. +.......................................................................... + +CONFIG_ARM64=y +CONFIG_ARCH_NXP=y +CONFIG_ARCH_S32=y +CONFIG_SOC_S32CC=y +CONFIG_SCHED_MC=y +CONFIG_ARM_SMMU=y + +CONFIG_NXP_GLOBAL_TIME_STM=y + +CONFIG_PINCTRL_S32CC=y +CONFIG_PINCTRL_SCMI=y + +CONFIG_CPU_IDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_ARM_SCMI_CPUFREQ=y + +CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y +#To keep align with SDK, unset the ARM_SCMI_POWER_DOMAIN config +# CONFIG_ARM_SCMI_POWER_DOMAIN is not set + +#CAN +CONFIG_CAN=y +CONFIG_CAN_VCAN=y +CONFIG_CAN_SLCAN=y +CONFIG_CAN_FLEXCAN=y + +#Ethernet +CONFIG_STMMAC_ETH=y +CONFIG_DWMAC_DWC_QOS_ETH=y +CONFIG_AT803X_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_AQUANTIA_PHY=y +CONFIG_BRIDGE=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_TAG_SJA1105=y +CONFIG_NXP_TJA11XX_PHY=y +CONFIG_NXP_C45_TJA11XX_PHY=y +CONFIG_NXP_CBTX_PHY=y +CONFIG_NET_DSA_SJA1105=y +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_BRIDGE_VLAN_FILTERING=y + +#Serial +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y + +#SPI +CONFIG_SPI=y +CONFIG_SPI_FSL_DSPI=y +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_S32CC=y +CONFIG_GPIO_SCMI=y +CONFIG_SENSORS_INA2XX=y + +#PCIE +CONFIG_PCI=y +CONFIG_PCI_S32CC=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCIEAER=y + +#USB +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_FSM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_ULPI_GENERIC=y + +#MMC +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_DMADEVICES=y +CONFIG_FSL_EDMA=y +CONFIG_CMA=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=128 + +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SPI_NOR=y +# In order to support UBI filesystem +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set + +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y + + +# Thermal +CONFIG_THERMAL=y +CONFIG_QORIQ_THERMAL=y +CONFIG_CPU_THERMAL=y + +# ADC +CONFIG_IIO=y +CONFIG_S32CC_ADC=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_FSL_FTM=y + +CONFIG_S32CC_FCCU=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y + +CONFIG_MDIO_DEVICE=y +CONFIG_PHYLIB=y + +#QSPI +CONFIG_SPI_FSL_QUADSPI=y + +#RTC +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S32CC=y +CONFIG_RTC_DRV_PCF85063=y + +#I2C +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_IMX=y + +#Watchdog +CONFIG_S32CC_WDT=y + +#NVME +CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_TARGET=y +CONFIG_NVMEM_S32CC_SIUL2=y +CONFIG_NVMEM_S32CC_OCOTP=y +CONFIG_NVMEM_S32CC_GPR=y +# CONFIG_NVMEM_SCMI is not set + +#LLCE +CONFIG_CAN_LLCE=y +CONFIG_CAN_LLCE_CONTROLLER=m + +# Regulator configuration +CONFIG_REGULATOR=y + +#HSE UIO +CONFIG_UIO=y +CONFIG_CRYPTO_DEV_NXP_HSE=y +CONFIG_UIO_NXP_HSE=y +CONFIG_UIO_NXP_HSE_MU0=y +CONFIG_CRYPTO_DEV_NXP_HSE_MU1=y + +#RANDOM +CONFIG_HW_RANDOM=y + +#OPTEE +CONFIG_TEE=y +CONFIG_OPTEE=y diff --git a/bsp/nxp-s32g/nxp-s32g.scc b/bsp/nxp-s32g/nxp-s32g.scc new file mode 100755 index 00000000..8674ac6b --- /dev/null +++ b/bsp/nxp-s32g/nxp-s32g.scc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: MIT +kconf hardware nxp-s32g.cfg + +include cfg/usb-mass-storage.scc + +include features/hugetlb/hugetlb.scc +include arch/arm/32bit-compat.scc -- 2.34.1
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