From: Jiang Lu <lu.ji...@windriver.com> Add device tree for ACP344x v2 board, the dts extracted from lsi_axxia_u-boot_4.8.1.78, with following modification: *Add nand flash partition info. *Add gpio, dma, i2c, ssp device info.
Signed-off-by: Jiang Lu <lu.ji...@windriver.com> --- arch/powerpc/boot/dts/ACP344xV2.dts | 487 ++++++++++++++++++++++++++++++++++++ 1 file changed, 487 insertions(+) create mode 100644 arch/powerpc/boot/dts/ACP344xV2.dts diff --git a/arch/powerpc/boot/dts/ACP344xV2.dts b/arch/powerpc/boot/dts/ACP344xV2.dts new file mode 100644 index 0000000..1a4040f --- /dev/null +++ b/arch/powerpc/boot/dts/ACP344xV2.dts @@ -0,0 +1,487 @@ +/* + * Device Tree Source for IBM Embedded PPC 476 Platform + * + * Copyright 2009 Torez Smith, IBM Corporation. + * + * Based on earlier code: + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer <jwbo...@linux.vnet.ibm.com>, David Gibson <d...@au1.ibm.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/memreserve/ 0x00000000 0x00400000; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "ibm,acpx1-4xx"; + compatible = "ibm,acpx1-4xx","ibm,47x-AMP"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + serial0 = &UART0; + serial1 = &UART1; + rapidio0 = &rio0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <0>; + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "ok"; + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + cpu@1 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <1>; + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + cpu@2 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <2>; + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + cpu@3 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <3>; + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000>; // filled in by U-Boot + }; + + MPIC: interrupt-controller { + compatible = "chrp,open-pic"; + interrupt-controller; + dcr-reg = <0xffc00000 0x00030000>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + pic-no-reset; + }; + + plb { + /* Could be PLB6, doesn't matter */ + compatible = "ibm,plb-4xx", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; // Filled in by zImage + + POB0: opb { + compatible = "ibm,opb-4xx", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Wish there was a nicer way of specifying a full 32-bit + range */ + ranges = <0x00000000 0x00000020 0x00000000 0x80000000 + 0x80000000 0x00000020 0x80000000 0x80000000>; + clock-frequency = <0>; // Filled in by zImage + UART0: serial@00404000 { + device_type = "serial"; + compatible = "acp-uart0"; + enabled = <0>; + reg = <0x00404000 0x1000>; + clock-reg = <0x00408040 0x20>; + clock-frequency = <200000000>; + current-speed = <9600>; + interrupt-parent = <&MPIC>; + interrupts = <22 2>; + }; + UART1: serial@00405000 { + device_type = "serial"; + compatible = "acp-uart1"; + enabled = <0>; + reg = <0x00405000 0x1000>; + clock-reg = <0x00408060 0x20>; + clock-frequency = <200000000>; + current-speed = <9600>; + interrupt-parent = <&MPIC>; + interrupts = <23 2>; + }; + USB0: usb@004a4000 { + device_type = "usb"; + compatible = "acp-usb"; + enabled = <0>; + reg = <0x004a0000 0x00020000 + 0x0040c000 0x00001000>; + interrupt-parent = <&MPIC>; + interrupts = <31 2>; + }; + I2C: i2c@00403000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "acp-i2c"; + enabled = <0>; + reg = <0x403000 0x1000 0x408020 0x1000>; + interrupt-parent = <&MPIC>; + interrupts = <21 2>; + + eeprom@50 { + compatible = "atmel,24c01"; + reg = <0x50>; + }; + }; + SSP: ssp@00402000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "acp-ssp"; + clock-frequency = <25000000>; + enabled = <1>; + reg = <0x00402000 0x00001000>; + interrupt-parent = <&MPIC>; + interrupts = <20 2>; + num-ss-bits = <5>; + enalbe-dma = <0>; + + eeprom@0{ + reg = <0>; + compatible = "at25"; + spi-max-frequency = <40000000>; /* input clock */ + }; + + eeprom@1{ + reg = <1>; + compatible = "at25"; + spi-max-frequency = <40000000>; /* input clock */ + }; + }; + NAND: nand@00440000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "nand"; + compatible = "acp-nand"; + enabled = <0>; + reg = <0x00440000 0x20000 + 0x0040c000 0x1000>; + + partition@0 { + /* This location must not be altered */ + /* 512KB for 2nd stage u-boot Bootloader Image */ + reg = <0x0 0x80000>; + label = "2nd Stage"; + read-only; + }; + + partition@80000 { + /* 512KB for u-boot variables */ + reg = <0x80000 0x80000>; + label = "env-0"; + read-only; + }; + + partition@100000 { + /* 512KB for u-boot variables */ + reg = <0x100000 0x80000>; + label = "env-1"; + read-only; + }; + + partition@180000 { + /* This location must not be altered */ + /* 512KB for 3rd stage u-boot Bootloader Image */ + reg = <0x180000 0x100000>; + label = "3rd Stage"; + read-only; + }; + + partition@280000 { + /* 6MB for Linux Image */ + reg = <0x0280000 0x580000>; + label = "linux"; + read-only; + }; + partition@800000 { + /* 1MB for Device Tree */ + reg = <0x0800000 0x100000>; + label = "linux_dtb"; + read-only; + }; + partition@900000 { + /* 497MB for Linux Rootfs*/ + reg = <0x900000 0x1F100000>; + label = "linux_fs"; + }; + partition@1FA00000 { + /* 32MB for OSE */ + reg = <0x1FA00000 0x2000000>; + label = "ose"; + read-only; + }; + partition@21A00000 { + /* 16MB for OSE backup*/ + reg = <0x21A00000 0x1000000>; + label = "ose backup"; + read-only; + }; + partition@22A00000 { + /* 470MB for OSE Storage*/ + reg = <0x22A00000 0x1D600000>; + label = "ose storage"; + }; + }; + FEMAC: femac@00480000 { + device_type = "network"; + compatible = "acp-femac"; + enabled = <0>; + reg = <0x00480000 0x1000 + 0x00481000 0x1000 + 0x00482000 0x1000>; + interrupt-parent = <&MPIC>; + interrupts = <33 2>; + mdio-reg = <0x00409000 0x1000>; + // The following will get filled in by + // the boot loader. + mdio-clock = <0>; + phy-address = <0>; + ad-value = <0>; + mac-address = [00 00 00 00 00 00]; + }; + + gpio@00400000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "amba_pl061"; + reg = <0x400000 0x1000>; + pins-map = <0x10>; /* GPIO 4 reserved for HW*/ + }; + + gpio@00401000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <8>; + compatible = "amba_pl061"; + reg = <0x401000 0x1000>; + pins-map = <0x29>; /* GPIO 8,11,13 reserved for HW*/ + }; + gpreg@0040c000 { + compatible = "lsi,gpreg"; + reg = <0x0040c000 0x1000>; + }; + gpdma@004e0000 { + compatible = "lsi,dma31"; + reg = <0x004e0000 0x20000>; + interrupt-parent = <&MPIC>; + channel0 { + interrupts = <35 2>; + }; + channel1 { + interrupts = <36 2>; + }; + channel2 { + interrupts = <37 2>; + }; + channel3 { + interrupts = <38 2>; + }; + }; + + }; + }; + + + nvrtc { + compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; + reg = <0 0xEF703000 0x2000>; + }; + + system { + ncr_0x00a_0x010_0x0002c = <0>; // filled in by the boot loader. + ncr_0x016_0x0ff_0x00010 = <0>; // filled in by the boot loader. + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@00404000"; + }; + + PCIE0: pciex@f00c0000 { + compatible = "lsi,plb-pciex"; + device_type = "pci"; + enabled = <0>; + plx = <0>; + primary; + port = <0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + /* config space access MPAGE7 registers*/ + reg = < 0x0020 0x78000000 0x01000000 + 0x0020 0x004c0000 0x00008000 >; + bus-range = <0 0x0f>; + /* Outbound ranges */ + /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */ + ranges = <0x02000000 0x00000000 0xa0000000 + 0x20 0x40000000 + 0x00 0x10000000>; + /* Inbound ranges */ + /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */ + dma-ranges = <0x02000000 0x00000000 0x00000000 + 0x00 0x00000000 + 0x00 0x10000000>; + interrupt-parent = <&MPIC>; + interrupts = <29 2>; + interrupt-map-mask = <0000 0 0 7>; + interrupt-map = < + /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */ + 0000 0 0 1 &MPIC 29 2 + 0000 0 0 2 &MPIC 29 2 + 0000 0 0 3 &MPIC 29 2 + 0000 0 0 4 &MPIC 29 2 + >; + }; + + PCIE1: pciex@f00c8000 { + compatible = "lsi,plb-pciex"; + device_type = "pci"; + enabled = <0>; + plx = <0>; + primary; + port = <1>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + /* config space access MPAGE7 registers*/ + reg = <0x0020 0xf8000000 0x01000000 + 0x0020 0x004c8000 0x00008000 >; + bus-range = <0 0x0f>; + /* Outbound ranges */ + /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */ + ranges = <0x02000000 0x00000000 0xa0000000 + 0x20 0xc0000000 + 0x00 0x10000000>; + /* Inbound ranges */ + /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */ + dma-ranges = <0x02000000 0x00000000 0x00000000 + 0x00 0x00000000 + 0x00 0x10000000>; + interrupt-parent = <&MPIC>; + interrupts = <72 2>; + interrupt-map-mask = <0000 0 0 7>; + interrupt-map = < + /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */ + 0000 0 0 1 &MPIC 72 2 + 0000 0 0 2 &MPIC 72 2 + 0000 0 0 3 &MPIC 72 2 + 0000 0 0 4 &MPIC 72 2 + >; + }; + + PCIE2: pciex@f00d0000 { + compatible = "lsi,plb-pciex"; + device_type = "pci"; + enabled = <0>; + plx = <0>; + primary; + port = <2>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + /* config space access MPAGE7 registers*/ + reg = <0x0021 0x38000000 0x01000000 + 0x0020 0x004d0000 0x00008000 >; + bus-range = <0 0x0f>; + /* Outbound ranges */ + /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */ + ranges = <0x02000000 0x00000000 0xa0000000 + 0x21 0x00000000 + 0x00 0x10000000>; + /* Inbound ranges */ + /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */ + dma-ranges = <0x02000000 0x00000000 0x00000000 + 0x00 0x00000000 + 0x00 0x10000000>; + + interrupt-parent = <&MPIC>; + interrupts = <73 2>; + interrupt-map-mask = <0000 0 0 7>; + interrupt-map = < + /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */ + 0000 0 0 1 &MPIC 73 2 + 0000 0 0 2 &MPIC 73 2 + 0000 0 0 3 &MPIC 73 2 + 0000 0 0 4 &MPIC 73 2 + >; + }; + + rio0: rapidio@f0020000 { + compatible = "acp,rapidio-delta"; + device_type = "rapidio"; + enabled = <0>; + #size = <0>; /* 0 = (256, small system) + * 1 = (65536, large system) */ +/* + #host-device-id = <1>; +*/ + /* >=0 for enum; < 0 for disc */ +/* + num-dme = <1 0 1>; +*/ + /* (#outb-mseg>, <#outb-sseg>, <#inb> */ +/* + num-odme-mseg-desc = <2 128 128>; + num-odme-sseg-desc = <1 256>; + num-idme-desc = <1 512>; +*/ + reg = <0xf0020000 0x20000 0x1000>; /* SRIO Conf region */ + interrupt-parent = <&MPIC>; + interrupts = <30 0x2 /* NCP_INTR_MPIC_SRC_AXIS_SRIO */>; + }; +}; -- 1.8.3 _______________________________________________ linux-yocto mailing list linux-yocto@yoctoproject.org https://lists.yoctoproject.org/listinfo/linux-yocto