From: "Chang, Rebecca Swee Fun" <rebecca.swee.fun.ch...@intel.com>
Remove PCI mode LPSS deivce configurations. These configurations are moved into a patch in recipe layer in order for Valley Island LPSS devices to support both ACPI mode and PCI mode enumeration. Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.ch...@intel.com> --- .../kernel-cache/features/valleyisland-io/valleyisland-io.cfg | 9 --------- 1 file changed, 9 deletions(-) diff --git a/meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io.cfg b/meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io.cfg index 983315b..a505cbd 100644 --- a/meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io.cfg +++ b/meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io.cfg @@ -1,12 +1,3 @@ -# By default, enable PCI mode enumeration -# change to "n" if to disable PCI mode -CONFIG_BYT_LPSS_BRD=y -CONFIG_GPIO_BYT_DEVICE=y -CONFIG_I2C_DESIGNWARE_PCI=y -CONFIG_SPI_PXA2XX_PCI=y -CONFIG_DW_DMAC_PCI=y -CONFIG_PWM_LPSS_PCI=y - #GPIO Support CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y -- 1.7.10.4 _______________________________________________ linux-yocto mailing list linux-yocto@yoctoproject.org https://lists.yoctoproject.org/listinfo/linux-yocto