From: John Jacques <john.jacq...@lsi.com> Also added the 6th Core to the Default 3500 Device Tree
Signed-off-by: John Jacques <john.jacq...@lsi.com> --- arch/powerpc/boot/dts/acp342x.dts | 347 +++++++++++++++++++------------------ arch/powerpc/boot/dts/acp344x.dts | 164 ++++++++++++------ arch/powerpc/boot/dts/acp35xx.dts | 73 ++++---- 3 files changed, 323 insertions(+), 261 deletions(-) diff --git a/arch/powerpc/boot/dts/acp342x.dts b/arch/powerpc/boot/dts/acp342x.dts index 6e02a8c..28a0a13 100644 --- a/arch/powerpc/boot/dts/acp342x.dts +++ b/arch/powerpc/boot/dts/acp342x.dts @@ -1,10 +1,10 @@ /* - * Device Tree Source for IBM Embedded PPC 476 Platform + * Device Tree Source for LSI Axxia ACP342x. * - * Copyright 2009 Torez Smith, IBM Corporation. + * Copyright 2013, LSI Corporation. * * Based on earlier code: - * Copyright (c) 2006, 2007 IBM Corp. + * Copyright (c) 2009, 2006, 2007 IBM Corp. * Josh Boyer <jwbo...@linux.vnet.ibm.com>, David Gibson <d...@au1.ibm.com> * * This file is licensed under the terms of the GNU General Public @@ -17,165 +17,187 @@ /memreserve/ 0x00000000 0x00400000; / { - #address-cells = <2>; - #size-cells = <1>; - model = "ibm,acpx1-4xx"; - compatible = "ibm,acpx1-4xx","ibm,47x-AMP"; - dcr-parent = <&{/cpus/cpu@0}>; - - aliases { - serial0 = &UART0; - serial1 = &UART1; - rapidio0 = &rio0; + #address-cells = <2>; + #size-cells = <1>; + model = "ibm,acpx1-4xx"; + compatible = "lsi,acp3420", "lsi,acp", "ibm,acpx1-4xx"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + serial0 = &UART0; + serial1 = &UART1; ethernet0 = &FEMAC; - }; + rapidio0 = &SRIO0; + }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - model = "PowerPC,4xx"; // real CPU changed in sim - reg = <0>; - clock-frequency = <0x5f5e1000>; - timebase-frequency = <0x5f5e1000>; - i-cache-line-size = <32>; - d-cache-line-size = <32>; - i-cache-size = <32768>; - d-cache-size = <32768>; - dcr-controller; - dcr-access-method = "native"; - status = "ok"; - reset-type = <3>; // 1=core, 2=chip, 3=system (default) - }; - }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <0>; + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "ok"; + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + + cpu@1 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <1>; + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // filled in by U-Boot + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + }; memory@0 { device_type = "memory"; - reg = <0x00000000 0x00000000 0x80000000>; // filled in by U-Boot + reg = <0 0 0>; // filled in by U-Boot }; memory@80000000 { device_type = "memory"; - reg = <0x00000000 0x80000000 0x80000000>; // filled in by U-Boot + reg = <0 0 0>; // filled in by U-Boot }; - MPIC: interrupt-controller { - compatible = "chrp,open-pic"; - interrupt-controller; - dcr-reg = <0xffc00000 0x00030000>; - #address-cells = <0>; - #size-cells = <0>; - #interrupt-cells = <2>; - pic-no-reset; - }; + MPIC: interrupt-controller { + compatible = "chrp,open-pic"; + interrupt-controller; + dcr-reg = <0xffc00000 0x00030000>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + pic-no-reset; + }; - plb { - /* Could be PLB6, doesn't matter */ - compatible = "ibm,plb-4xx", "ibm,plb4"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - clock-frequency = <0>; // Filled in by zImage - - POB0: opb { - compatible = "ibm,opb-4xx", "ibm,opb"; - #address-cells = <1>; - #size-cells = <1>; - /* Wish there was a nicer way of specifying a full 32-bit - range */ - ranges = <0x00000000 0x00000020 0x00000000 0x80000000 - 0x80000000 0x00000020 0x80000000 0x80000000>; - clock-frequency = <0>; // Filled in by zImage - UART0: serial@00404000 { - device_type = "serial"; - compatible = "lsi,acp-uart0"; - enabled = <1>; - reg = <0x00404000 0x1000>; - clock-reg = <0x00408040 0x20>; - clock-frequency = <0xbebc200>; - current-speed = <9600>; - interrupt-parent = <&MPIC>; - interrupts = <22>; - }; - UART1: serial@00405000 { - device_type = "serial"; - compatible = "lsi,acp-uart1"; - enabled = <0>; - reg = <0x00405000 0x1000>; - clock-reg = <0x00408060 0x20>; - clock-frequency = <200000000>; - current-speed = <9600>; - interrupt-parent = <&MPIC>; - interrupts = <23>; - }; - USB0: usb@004a4000 { - device_type = "usb"; - compatible = "lsi,acp-usb"; - enabled = <1>; - reg = <0x20 0x004A0000 0x0 0020000>, - <0x20 0x0040C000 0x0 0001000>; - interrupt-parent = <&MPIC>; - interrupts = <31>; - }; - I2C: i2c@00403000 { - compatible = "lsi,acp-i2c"; - enabled = <0>; - reg = <0x00403000 0x00001000>; - interrupt-parent = <&MPIC>; - interrupts = <21>; - }; - SSP: ssp@00402000 { - compatible = "arm,acp-ssp"; - enabled = <0>; - reg = <0x00402000 0x00001000>; - interrupt-parent = <&MPIC>; - interrupts = <20>; - }; - NAND: nand@00440000 { - device_type = "nand"; - compatible = "lsi,acp-nand"; - enabled = <1>; - reg = <0x00440000 0x20000 - 0x0040c000 0x1000>; - }; - FEMAC: femac@00480000 { - device_type = "network"; - compatible = "lsi,acp-femac"; - enabled = <1>; - reg = <0x00480000 0x1000 - 0x00481000 0x1000 - 0x00482000 0x1000>; - interrupt-parent = <&MPIC>; - interrupts = <33>; - mdio-reg = <0x00409000 0x1000>; - // The following will get filled in by - // the boot loader. - mdio-clock = <0>; - phy-address = <0>; - ad-value = <0>; - mac-address = [00 00 00 00 00 00]; - }; - }; - }; + plb { + /* Could be PLB6, doesn't matter */ + compatible = "ibm,plb-4xx", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; // Filled in by zImage + POB0: opb { + compatible = "ibm,opb-4xx", "ibm,opb"; - nvrtc { - compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; - reg = <0 0xEF703000 0x2000>; - }; + #address-cells = <1>; + #size-cells = <1>; - system { - ncr_0x00a_0x010_0x0002c = <0>; // filled in by the boot loader. - ncr_0x016_0x0ff_0x00010 = <0>; // filled in by the boot loader. - }; + /* Wish there was a nicer way of specifying a full 32-bit + range */ - chosen { - linux,stdout-path = "/plb/opb/serial@00404000"; - }; + ranges = <0x00000000 0x00000020 0x00000000 0x80000000 + 0x80000000 0x00000020 0x80000000 0x80000000>; + + clock-frequency = <0>; // Filled in by zImage + + UART0: serial0 { + device_type = "serial"; + compatible = "acp-uart0"; + reg = <0x00404000 0x1000>; + clock-reg = <0x00408040 0x20>; + clock-frequency = <200000000>; + current-speed = <9600>; + interrupt-parent = <&MPIC>; + interrupts = <22>; + }; + + UART1: serial1 { + device_type = "serial"; + compatible = "acp-uart1"; + reg = <0x00405000 0x1000>; + clock-reg = <0x00408060 0x20>; + clock-frequency = <200000000>; + current-speed = <9600>; + interrupt-parent = <&MPIC>; + interrupts = <23>; + }; + + USB0: usb0 { + device_type = "usb"; + compatible = "acp-usb"; + reg = <0x004a0000 0x00020000 + 0x0040c000 0x00001000>; + interrupt-parent = <&MPIC>; + interrupts = <31 2>; + }; - PCIE0: pciex@f00c0000 { + I2C: i2c0 { + compatible = "acp-i2c"; + reg = <0x00403000 0x00001000>; + interrupt-parent = <&MPIC>; + interrupts = <21>; + }; + + SSP: ssp0 { + compatible = "acp-ssp"; + reg = <0x00402000 0x00001000>; + interrupt-parent = <&MPIC>; + interrupts = <20>; + }; + + NAND: nand0 { + device_type = "nand"; + compatible = "acp-nand"; + reg = <0x00440000 0x20000 + 0x0040c000 0x1000>; + }; + + FEMAC: femac0 { + device_type = "network"; + compatible = "acp-femac"; + reg = <0x00480000 0x1000 + 0x00481000 0x1000 + 0x00482000 0x1000>; + interrupt-parent = <&MPIC>; + interrupts = <33>; + mdio-reg = <0x00409000 0x1000>; + // The following will get filled in by + // the boot loader. + mdio-clock = <0>; + phy-address = <0>; + ad-value = <0>; + mac-address = [00 00 00 00 00 00]; + }; + }; + }; + + + nvrtc { + compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; + reg = <0 0xEF703000 0x2000>; + }; + + system { + ncr_0x00a_0x010_0x0002c = <0>; // filled in by the boot loader. + ncr_0x016_0x0ff_0x00010 = <0>; // filled in by the boot loader. + }; + + chosen { + linux,stdout-path = "/plb/opb/serial0"; + }; + + PCIE0: pei0 { compatible = "lsi,plb-pciex"; device_type = "pci"; enabled = <0>; @@ -186,7 +208,7 @@ #size-cells = <2>; #address-cells = <3>; /* config space access MPAGE7 registers*/ - reg = < 0x0020 0x78000000 0x01000000 + reg = <0x0020 0x78000000 0x01000000 0x0020 0x004c0000 0x00008000 >; bus-range = <0 0x0f>; /* Outbound ranges */ @@ -211,7 +233,7 @@ >; }; - PCIE1: pciex@f00c8000 { + PCIE1: pei1 { compatible = "lsi,plb-pciex"; device_type = "pci"; enabled = <0>; @@ -227,7 +249,7 @@ bus-range = <0 0x0f>; /* Outbound ranges */ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */ - ranges = <0x02000000 0x00000000 0xa0000000 + ranges = <0x02000000 0x00000000 0xb0000000 0x20 0xc0000000 0x00 0x10000000>; /* Inbound ranges */ @@ -247,7 +269,7 @@ >; }; - PCIE2: pciex@f00d0000 { + PCIE2: pei2 { compatible = "lsi,plb-pciex"; device_type = "pci"; enabled = <0>; @@ -263,7 +285,7 @@ bus-range = <0 0x0f>; /* Outbound ranges */ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */ - ranges = <0x02000000 0x00000000 0xa0000000 + ranges = <0x02000000 0x00000000 0xc0000000 0x21 0x00000000 0x00 0x10000000>; /* Inbound ranges */ @@ -284,22 +306,15 @@ >; }; - rio0: rapidio@0x2080000000 { - index = <0>; - status = "okay"; - #address-cells = <2>; - #size-cells = <2>; - compatible = "axxia,rapidio-delta"; + SRIO0: srio0 { + compatible = "acp,rapidio-delta"; device_type = "rapidio"; - reg = <0x0020 0x00420000 0x1000>; /* SRIO Conf 0 region */ - ranges = <0x0 0x0 0x0020 0x80000000 0x0 0x40000000>; - /* - linkdown-reset = <0x0200 0x100 0x0020 0x00430000 0x0 0x000010000>; - */ + enabled = <0>; + #size = <0>; /* 0 = (256, small system) + * 1 = (65536, large system) */ + /* >=0 for enum; < 0 for disc */ + reg = <0xf0020000 0x20000 0x1000>; /* SRIO Conf region */ interrupt-parent = <&MPIC>; - interrupts = <30 2>; - outb-dmes = <2 0x00000003 1 0x00000001>; - enable_ds = <1>; - }; - + interrupts = <30 0x2 /* NCP_INTR_MPIC_SRC_AXIS_SRIO */>; + }; }; diff --git a/arch/powerpc/boot/dts/acp344x.dts b/arch/powerpc/boot/dts/acp344x.dts index 2c25007..9ade880 100644 --- a/arch/powerpc/boot/dts/acp344x.dts +++ b/arch/powerpc/boot/dts/acp344x.dts @@ -1,10 +1,10 @@ /* - * Device Tree Source for IBM Embedded PPC 476 Platform + * Device Tree Source for LSI Axxia ACP344x V2. * - * Copyright 2009 Torez Smith, IBM Corporation. + * Copyright 2013 LSI Corporation. * * Based on earlier code: - * Copyright (c) 2006, 2007 IBM Corp. + * Copyright (c) 2009, 2006, 2007 IBM Corp. * Josh Boyer <jwbo...@linux.vnet.ibm.com>, David Gibson <d...@au1.ibm.com> * * This file is licensed under the terms of the GNU General Public @@ -19,15 +19,16 @@ / { #address-cells = <2>; #size-cells = <1>; + model = "ibm,acpx1-4xx"; - compatible = "ibm,acpx1-4xx","ibm,47x-AMP"; + compatible = "lsi,acp3440", "lsi,acp", "ibm,acpx1-4xx"; dcr-parent = <&{/cpus/cpu@0}>; aliases { - serial0 = &UART0; - serial1 = &UART1; - rapidio0 = &rio0; + serial0 = &UART0; + serial1 = &UART1; ethernet0 = &FEMAC; + rapidio0 = &SRIO0; }; cpus { @@ -38,8 +39,8 @@ device_type = "cpu"; model = "PowerPC,4xx"; // real CPU changed in sim reg = <0>; - clock-frequency = <0x5f5e1000>; - timebase-frequency = <0x5f5e1000>; + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot i-cache-line-size = <32>; d-cache-line-size = <32>; i-cache-size = <32768>; @@ -49,16 +50,70 @@ status = "ok"; reset-type = <3>; // 1=core, 2=chip, 3=system (default) }; + + cpu@1 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <1>; + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + + cpu@2 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <2>; + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + + cpu@3 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <3>; + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; }; memory@0 { device_type = "memory"; - reg = <0x00000000 0x00000000 0x80000000>; // filled in by U-Boot + reg = <0 0 0>; // filled in by U-Boot }; memory@80000000 { device_type = "memory"; - reg = <0x00000000 0x80000000 0x80000000>; // filled in by U-Boot + reg = <0 0 0>; // filled in by U-Boot }; MPIC: interrupt-controller { @@ -77,31 +132,36 @@ #address-cells = <2>; #size-cells = <1>; ranges; - clock-frequency = <0>; // Filled in by zImage + clock-frequency = <0>; POB0: opb { compatible = "ibm,opb-4xx", "ibm,opb"; + #address-cells = <1>; #size-cells = <1>; + /* Wish there was a nicer way of specifying a full 32-bit range */ ranges = <0x00000000 0x00000020 0x00000000 0x80000000 0x80000000 0x00000020 0x80000000 0x80000000>; - clock-frequency = <0>; // Filled in by zImage - UART0: serial@00404000 { + + clock-frequency = <0>; + + UART0: serial0 { device_type = "serial"; - compatible = "lsi,acp-uart0"; - enabled = <1>; + compatible = "acp-uart0"; + enabled = <0>; reg = <0x00404000 0x1000>; clock-reg = <0x00408040 0x20>; - clock-frequency = <0xbebc200>; + clock-frequency = <200000000>; current-speed = <9600>; interrupt-parent = <&MPIC>; interrupts = <22>; }; - UART1: serial@00405000 { + + UART1: serial1 { device_type = "serial"; - compatible = "lsi,acp-uart1"; + compatible = "acp-uart1"; enabled = <0>; reg = <0x00405000 0x1000>; clock-reg = <0x00408060 0x20>; @@ -110,39 +170,45 @@ interrupt-parent = <&MPIC>; interrupts = <23>; }; - USB0: usb@004a4000 { + + USB0: usb0 { device_type = "usb"; - compatible = "lsi,acp-usb"; + compatible = "acp-usb"; enabled = <0>; - reg = <0x004a4000 0x00020000>; + reg = <0x004a0000 0x00020000 + 0x0040c000 0x00001000>; interrupt-parent = <&MPIC>; - interrupts = <31>; + interrupts = <31 2>; }; - I2C: i2c@00403000 { - compatible = "lsi,acp-i2c"; + + I2C: i2c0 { + compatible = "acp-i2c"; enabled = <0>; reg = <0x00403000 0x00001000>; interrupt-parent = <&MPIC>; interrupts = <21>; }; - SSP: ssp@00402000 { - compatible = "arm,acp-ssp"; + + SSP: ssp0 { + compatible = "acp-ssp"; enabled = <0>; reg = <0x00402000 0x00001000>; interrupt-parent = <&MPIC>; interrupts = <20>; }; - NAND: nand@00440000 { + + NAND: nand0 { device_type = "nand"; - compatible = "lsi,acp-nand"; - enabled = <1>; + compatible = "acp-nand"; + enabled = <0>; reg = <0x00440000 0x20000 0x0040c000 0x1000>; }; - FEMAC: femac@00480000 { + + FEMAC: femac0 { device_type = "network"; - compatible = "lsi,acp-femac"; - enabled = <1>; + compatible = "acp-femac"; + enabled = <0>; reg = <0x00480000 0x1000 0x00481000 0x1000 0x00482000 0x1000>; @@ -171,10 +237,10 @@ }; chosen { - linux,stdout-path = "/plb/opb/serial@00404000"; + linux,stdout-path = "/plb/opb/serial0"; }; - PCIE0: pciex@f00c0000 { + PCIE0: pei0 { compatible = "lsi,plb-pciex"; device_type = "pci"; enabled = <0>; @@ -210,7 +276,7 @@ >; }; - PCIE1: pciex@f00c8000 { + PCIE1: pei1 { compatible = "lsi,plb-pciex"; device_type = "pci"; enabled = <0>; @@ -246,7 +312,7 @@ >; }; - PCIE2: pciex@f00d0000 { + PCIE2: pei2 { compatible = "lsi,plb-pciex"; device_type = "pci"; enabled = <0>; @@ -283,22 +349,14 @@ >; }; - rio0: rapidio@0x2080000000 { - index = <0>; - status = "okay"; - #address-cells = <2>; - #size-cells = <2>; - compatible = "axxia,rapidio-delta"; + SRIO0: srio0 { + compatible = "acp,rapidio-delta"; device_type = "rapidio"; - reg = <0x0020 0x00420000 0x1000>; /* SRIO Conf 0 region */ - ranges = <0x0 0x0 0x0020 0x80000000 0x0 0x40000000>; - /* - linkdown-reset = <0x0200 0x100 0x0020 0x00430000 0x0 0x000010000>; - */ - interrupt-parent = <&MPIC>; - interrupts = <30 2>; - outb-dmes = <2 0x00000003 1 0x00000001>; - enable_ds = <1>; + enabled = <0>; + #size = <0>; /* 0 = (256, small system) + * 1 = (65536, large system) */ + reg = <0xf0020000 0x20000 0x1000>; /* SRIO Conf region */ + interrupt-parent = <&MPIC>; + interrupts = <30 0x2 /* NCP_INTR_MPIC_SRC_AXIS_SRIO */>; }; - }; diff --git a/arch/powerpc/boot/dts/acp35xx.dts b/arch/powerpc/boot/dts/acp35xx.dts index 0bf153f..1ac95b1 100644 --- a/arch/powerpc/boot/dts/acp35xx.dts +++ b/arch/powerpc/boot/dts/acp35xx.dts @@ -20,14 +20,14 @@ #address-cells = <2>; #size-cells = <1>; model = "ibm,acpx1-4xx"; - compatible = "ibm,acpx1-4xx","ibm,47x-AMP"; + compatible = "lsi,acp3500", "lsi,axxia35xx", "lsi,acp", "ibm,acpx1-4xx"; dcr-parent = <&{/cpus/cpu@0}>; aliases { serial0 = &UART0; serial1 = &UART1; ethernet0 = &FEMAC; - rapidio0 = &rio0; + rapidio0 = &SRIO0; }; cpus { @@ -38,8 +38,8 @@ device_type = "cpu"; model = "PowerPC,4xx"; // real CPU changed in sim reg = <0>; - clock-frequency = <0x5f5e1000>; // filled in by U-Boot - timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot i-cache-line-size = <32>; d-cache-line-size = <32>; i-cache-size = <32768>; @@ -54,8 +54,8 @@ device_type = "cpu"; model = "PowerPC,4xx"; // real CPU changed in sim reg = <1>; - clock-frequency = <0x5f5e1000>; // filled in by U-Boot - timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot i-cache-line-size = <32>; d-cache-line-size = <32>; i-cache-size = <32768>; @@ -64,7 +64,7 @@ dcr-access-method = "native"; status = "disabled"; enable-method = "spin-table"; - cpu-release-addr = <0 0>; // Fixed by the boot loader + cpu-release-addr = <0>; // filled in by U-Boot reset-type = <3>; // 1=core, 2=chip, 3=system (default) }; @@ -72,8 +72,8 @@ device_type = "cpu"; model = "PowerPC,4xx"; // real CPU changed in sim reg = <2>; - clock-frequency = <0x5f5e1000>; // filled in by U-Boot - timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot i-cache-line-size = <32>; d-cache-line-size = <32>; i-cache-size = <32768>; @@ -82,7 +82,7 @@ dcr-access-method = "native"; status = "disabled"; enable-method = "spin-table"; - cpu-release-addr = <0 0>; // Fixed by the boot loader + cpu-release-addr = <0>; // filled in by U-Boot reset-type = <3>; // 1=core, 2=chip, 3=system (default) }; @@ -91,8 +91,8 @@ device_type = "cpu"; model = "PowerPC,4xx"; // real CPU changed in sim reg = <3>; - clock-frequency = <0x5f5e1000>; // filled in by U-Boot - timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot i-cache-line-size = <32>; d-cache-line-size = <32>; i-cache-size = <32768>; @@ -101,16 +101,16 @@ dcr-access-method = "native"; status = "disabled"; enable-method = "spin-table"; - cpu-release-addr = <0 0>; // Fixed by the boot loader + cpu-release-addr = <0>; // filled in by U-Boot reset-type = <3>; // 1=core, 2=chip, 3=system (default) }; - cpu@4 { + cpu@4 { device_type = "cpu"; model = "PowerPC,4xx"; // real CPU changed in sim reg = <4>; - clock-frequency = <0x5f5e1000>; // filled in by U-Boot - timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot i-cache-line-size = <32>; d-cache-line-size = <32>; i-cache-size = <32768>; @@ -119,16 +119,16 @@ dcr-access-method = "native"; status = "disabled"; enable-method = "spin-table"; - cpu-release-addr = <0 0>; // Fixed by the boot loader + cpu-release-addr = <0>; // filled in by U-Boot reset-type = <3>; // 1=core, 2=chip, 3=system (default) }; - cpu@5 { + cpu@5 { device_type = "cpu"; model = "PowerPC,4xx"; // real CPU changed in sim reg = <5>; - clock-frequency = <0x5f5e1000>; // filled in by U-Boot - timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + clock-frequency = <0>; // filled in by U-Boot + timebase-frequency = <0>; // filled in by U-Boot i-cache-line-size = <32>; d-cache-line-size = <32>; i-cache-size = <32768>; @@ -137,22 +137,19 @@ dcr-access-method = "native"; status = "disabled"; enable-method = "spin-table"; - cpu-release-addr = <0 0>; // Fixed by the boot loader + cpu-release-addr = <0>; // filled in by U-Boot reset-type = <3>; // 1=core, 2=chip, 3=system (default) }; - - - }; memory@0 { device_type = "memory"; - reg = <0x00000000 0x00000000 0x08000000>; // filled in by U-Boot + reg = <0 0 0>; // filled in by U-Boot }; memory@80000000 { device_type = "memory"; - reg = <0x00000000 0x08000000 0x08000000>; // filled in by U-Boot + reg = <0 0 0>; // filled in by U-Boot }; MPIC: interrupt-controller { @@ -394,22 +391,14 @@ >; }; - rio0: rapidio@0x2100000000 { - index = <0>; - status = "okay"; - #address-cells = <2>; - #size-cells = <2>; - compatible = "axxia,rapidio-delta"; + SRIO0: srio0 { + compatible = "acp,rapidio-delta"; device_type = "rapidio"; - reg = <0x0020 0x00560000 0x1000>; /* SRIO Conf 0 region */ - ranges = <0x0 0x0 0x0021 0x00000000 0x0 0x40000000>; - /* - linkdown-reset = <0x0200 0x100 0x0020 0x0040A000 0x0 0x000010000>; - */ + enabled = <0>; + #size = <0>; /* 0 = (256, small system) + * 1 = (65536, large system) */ + reg = <0xf0020000 0x20000 0x1000>; /* SRIO Conf region */ interrupt-parent = <&MPIC>; - interrupts = <56 2>; - outb-dmes = <2 0x00000003 1 0x00000001>; - enable_ds = <1>; - }; -+ + interrupts = <56 0x2 /* NCP_INTR_MPIC_SRC_AXIS_SRIO */>; + }; }; -- 1.7.9.5 -- _______________________________________________ linux-yocto mailing list linux-yocto@yoctoproject.org https://lists.yoctoproject.org/listinfo/linux-yocto