[linux-yocto] [PATCH 08/12] MIPS: OCTEON: Move L2 Cache probing code to setup.c

[Chandrakala Chavva]

From: Abhishek Paliwal <abhishek.pali...@aricent.com>

From: David Daney <david.da...@cavium.com>

When we run as a virtualized guest kernel, the CPU is disassociated
from the OCTEON SoC's L2 cache, so we move the corresponding code to a
SoC specific place.  This allows us to share c-octeon.c between both
Normal and VM cases.

Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Abhishek Paliwal <abhishek.pali...@aricent.com>
---
 arch/mips/cavium-octeon/setup.c       | 22 ++++++++++++++++++++++
 arch/mips/include/asm/octeon/octeon.h |  3 +++
 arch/mips/mm/c-octeon.c               |  3 +++
 3 files changed, 28 insertions(+)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 83355fb..50838ff 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -51,6 +51,7 @@ extern void pci_console_init(const char *arg);
 
 static unsigned long long MAX_MEMORY = 512ull << 20;
 
+DEFINE_SEMAPHORE(octeon_bootbus_sem);
 struct octeon_boot_descriptor *octeon_boot_desc_ptr;
 
 struct cvmx_bootinfo *octeon_bootinfo;
@@ -618,6 +619,25 @@ void octeon_user_io_init(void)
        write_c0_derraddr1(0);
 }
 
+static void octeon_soc_scache_init(void)
+{
+       struct cpuinfo_mips *c = &current_cpu_data;
+       unsigned long scache_size = cvmx_l2c_get_cache_size_bytes();
+
+       c->scache.sets = cvmx_l2c_get_num_sets();
+       c->scache.ways = cvmx_l2c_get_num_assoc();
+       c->scache.waybit = ffs(scache_size / c->scache.ways) - 1;
+       c->scache.waysize = scache_size / c->scache.ways;
+       c->scache.linesz = 128;
+       c->scache.flags |= MIPS_CPU_PREFETCH;
+
+       c->tcache.flags |= MIPS_CACHE_NOT_PRESENT;
+
+       if (smp_processor_id() == 0)
+               pr_notice("Secondary unified cache %ldkB, %d-way, %d sets, 
linesize %d bytes.\n",
+                               scache_size >> 10, c->scache.ways,
+                               c->scache.sets, c->scache.linesz);
+}
 /**
  * Early entry point for arch setup
  */
@@ -628,6 +648,8 @@ void __init prom_init(void)
        char *p;
        int i;
        int argc;
+
+       octeon_scache_init = octeon_soc_scache_init;
 #ifdef CONFIG_CAVIUM_RESERVE32
        int64_t addr = -1;
 #endif
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index dc42317..3500bdd 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -270,6 +270,9 @@ extern void octeon_fixup_irqs(void);
 
 int octeon_i2c_cvmx2i2c(unsigned int cvmx_twsi_bus_num);
 
+extern struct semaphore octeon_bootbus_sem;
+
+extern void (*octeon_scache_init)(void);
 int register_co_cache_error_notifier(struct notifier_block *nb);
 int unregister_co_cache_error_notifier(struct notifier_block *nb);
 #define CO_CACHE_ERROR_RECOVERABLE 0
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index c0a0fb4..3fe97f5 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -320,6 +320,7 @@ static int octeon3_mcheck_handler(struct pt_regs *regs)
        return MIPS_MC_NOT_HANDLED;
 }
 
+void (*octeon_scache_init)(void);
 /**
  * Probe Octeon's caches
  *
@@ -414,6 +415,8 @@ static void probe_octeon(void)
                          dcache_size >> 10, c->dcache.ways,
                          c->dcache.sets, c->dcache.linesz);
        }
+       if (octeon_scache_init)
+               octeon_scache_init();
 }
 
 static void  octeon_cache_error_setup(void)
-- 
1.8.1.4

-- 
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