From: SangeethaRao <sangeetha....@intel.com>
The support was updated to use DTS entries.
PCIe legacy ISR is updated to not mask link
alarms since this doesn't apply to AXM55xx
Signed-off-by: SangeethaRao <sangeetha....@intel.com>
---
arch/arm/boot/dts/axm55xx.dtsi | 4 +++-
arch/arm/mach-axxia/pci.c | 17 +++++------------
2 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
index 2d1771b..72ed71f 100644
--- a/arch/arm/boot/dts/axm55xx.dtsi
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -196,6 +196,7 @@
0x00 0x00000000
0x00 0x40000000>;
interrupts = <0 68 4>,
+ <0 71 4>,
<0 73 4>,
<0 74 4>,
<0 75 4>,
@@ -235,7 +236,8 @@
dma-ranges = <0x03000000 0x00000000 0x00000000
0x00 0x00000000
0x00 0x40000000>;
- interrupts = <0 70 4>;
+ interrupts = <0 70 4>,
+ <0 72 4>;
port = <1>;
status = "disabled";
};
diff --git a/arch/arm/mach-axxia/pci.c b/arch/arm/mach-axxia/pci.c
index 08978ec..abb3664 100644
--- a/arch/arm/mach-axxia/pci.c
+++ b/arch/arm/mach-axxia/pci.c
@@ -119,7 +119,7 @@ struct axxia_pciex_port {
unsigned int index;
u8 root_bus_nr;
bool link_up;
- int irq[17]; /* 1 legacy, 16 MSI */
+ int irq[18]; /* 1 legacy, 1 Doorbell (EP), 16 MSI */
void __iomem *regs;
void __iomem *cfg_data;
u32 last_mpage;
@@ -466,17 +466,11 @@ pcie_legacy_isr(int irq, void *arg)
if (intr_status & 0x00020000) {
pr_info("PCIE%d: t2a_fn_indp_err_stat = %#x\n",
port->index, readl(mbase+0x1170));
- int_enb = readl(mbase + PCIE_INT0_ENABLE);
- int_enb &= 0xfffdffff;
- writel(int_enb, mbase + PCIE_INT0_ENABLE);
}
if (intr_status & 0x00040000) {
pr_info("PCIE%d: t2a_fn_indp_other_err_stat =
%#x\n",
port->index, readl(mbase+0x1174));
- int_enb = readl(mbase + PCIE_INT0_ENABLE);
- int_enb &= 0xfffbffff;
- writel(int_enb, mbase + PCIE_INT0_ENABLE);
}
if (intr_status & 0x00000800) {
@@ -484,9 +478,6 @@ pcie_legacy_isr(int irq, void *arg)
port->index,
readl(mbase + PCIE_CONFIG),
readl(mbase + PCIE_STATUS));
- int_enb = readl(mbase + PCIE_INT0_ENABLE);
- int_enb &= 0xfffff7ff;
- writel(int_enb, mbase + PCIE_INT0_ENABLE);
}
/*
@@ -693,7 +684,8 @@ static int axxia_pcie_setup(int portno, struct pci_sys_data
*sys)
pr_err("PCIE%d: Device is not Root Complex\n", port->index);
if (sys->domain == 0) {
/* PEI0 */
- err = request_irq(port->irq[0]+3, pcie_doorbell_isr,
+ port->irq[1] = irq_of_parse_and_map(port->node, 1);
+ err = request_irq(port->irq[1], pcie_doorbell_isr,
IRQF_SHARED, "pcie_db", port);
if (err) {
pr_err("PCIE%d: Failed to request IRQ#%d
(%d)\n",
@@ -703,7 +695,8 @@ static int axxia_pcie_setup(int portno, struct pci_sys_data
*sys)
}
} else if (sys->domain == 1) {
/* PEI1 */
- err = request_irq(port->irq[0]+2, pcie_doorbell_isr,
+ port->irq[1] = irq_of_parse_and_map(port->node, 1);
+ err = request_irq(port->irq[1], pcie_doorbell_isr,
IRQF_SHARED, "pcie_db", port);
if (err) {
pr_err("PCIE%d: Failed to request IRQ#%d
(%d)\n",
--
1.7.9.5
--
_______________________________________________
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto
