From: Paul Butler <paul.but...@windriver.com> Signed-off-by: Paul Butler <paul.but...@windriver.com> --- arch/arm/boot/dts/axm55xx.dts | 8 +- drivers/misc/lsi-mtc.c | 1375 ++++++++++++++++++++--------------------- 2 files changed, 694 insertions(+), 689 deletions(-)
diff --git a/arch/arm/boot/dts/axm55xx.dts b/arch/arm/boot/dts/axm55xx.dts index 07a3cb4..72cc760 100644 --- a/arch/arm/boot/dts/axm55xx.dts +++ b/arch/arm/boot/dts/axm55xx.dts @@ -1,5 +1,5 @@ /* - * arch/arm/boot/dts/axm5500-sim.dts + * arch/arm/boot/dts/axm5500.dts * * Copyright (C) 2012 LSI * @@ -321,6 +321,12 @@ reg = <0x20 0x10087000 0x00 0x1000>; interrupts = <0 22 4>; }; + + mtc@2010098000 { + compatible = "lsi,mtc"; + reg = <0x20 0x10098000 0 0x3000>; + interrupts = <0 45 4>; + }; }; /* diff --git a/drivers/misc/lsi-mtc.c b/drivers/misc/lsi-mtc.c index dcef03e..d31a64e 100644 --- a/drivers/misc/lsi-mtc.c +++ b/drivers/misc/lsi-mtc.c @@ -31,6 +31,7 @@ #include <linux/string.h> #include "linux/lsi_mtc_ioctl.h" +#define DEBUG /* device tree node: @@ -43,7 +44,6 @@ */ - /* MTC registers */ struct mtc_regs { u32 params; /* 0x00 */ @@ -79,26 +79,23 @@ struct mtc_regs { #define MTC_PRGMEM_OFFSET 0x1000 #define MTC_TDOMEM_OFFSET 0x2000 -#define MTC_PRGMEM_SIZE 256 /* program memory size in words */ -#define MTC_TDOMEM_SIZE 256 /* tdo memory size in words */ - +#define MTC_PRGMEM_SIZE 256 /* program memory size in words */ +#define MTC_TDOMEM_SIZE 256 /* tdo memory size in words */ #ifdef __MTC_SIMULATION - struct mtc_regs _mtc_regs; - u32 _mtc_tdomem[256] = {0x11110000, 0x22221111, 0x33332222}; - u32 *_mtc_prgmem = _mtc_tdomem; - -#endif +struct mtc_regs _mtc_regs; +u32 _mtc_tdomem[256] = { 0x11110000, 0x22221111, 0x33332222 }; +u32 *_mtc_prgmem = _mtc_tdomem; +#endif /******************************************************/ /* register definitions generated from RDL */ /******************************************************/ - /* NODE 0x15d , TARGET 0xffffffff*/ - + /* NODE 0x15d , TARGET 0xffffffff */ #define NCP_AXIS_MTC_MTC_INST_PARAMS0_REG_ADDR (0x00000000) #define NCP_AXIS_MTC_MTC_SCRATCH0_REG_ADDR (0x00000004) @@ -123,22 +120,21 @@ struct mtc_regs { #define NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR(n) (0x00001000 + (4*(n))) #define NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR_COUNT (0x00000100) #define NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR_IDX(addr) \ - (((addr) - NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR_BASE) / 4) + (((addr) - NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR_BASE) / 4) #define NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR_END (0x00001400) #define NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR_RANGE(addr) \ - (((addr) >= NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR_BASE) && \ - ((addr) < NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR_END)) - + (((addr) >= NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR_BASE) && \ + ((addr) < NCP_AXIS_MTC_MTC_PRGM_MEM_START_ADDR_END)) #define NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_BASE (0x00002000) #define NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR(n) (0x00002000 + (4*(n))) #define NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_COUNT (0x00000100) #define NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_IDX(addr) \ - (((addr) - NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_BASE) / 4) + (((addr) - NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_BASE) / 4) #define NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_END (0x00002400) #define NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_RANGE(addr) \ - (((addr) >= NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_BASE) && \ - ((addr) < NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_END)) + (((addr) >= NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_BASE) && \ + ((addr) < NCP_AXIS_MTC_MTC_TDO_CAPTURE_MEM_START_ADDR_END)) #define NCP_AXIS_MTC_MTC_TSTGEN_INT_STATUS (0x00000050) #define NCP_AXIS_MTC_MTC_TSTGEN_INT_STATUS_ALARM_MASK (0x0000007f) @@ -153,8 +149,6 @@ struct mtc_regs { #define NCP_AXIS_MTC_MTC_ECC_INT_FRC (0x00000064) #define NCP_AXIS_MTC_MTC_ECC_INT_FRC_ALARM_MASK (0x0000000f) - - /*! @struct ncp_axis_mtc_MTC_INST_PARAMS0_REG_ADDR_r_t * @brief MTC Parameter Register * @details null @@ -199,17 +193,17 @@ struct mtc_regs { * */ -struct ncp_axis_mtc_MTC_INST_PARAMS0_REG_ADDR_r_t{ +struct ncp_axis_mtc_MTC_INST_PARAMS0_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:6; - unsigned tdo_memory_size:10; - unsigned reserved1:6; - unsigned tst_prgm_memory_size:10; -#else /* Little Endian */ - unsigned tst_prgm_memory_size:10; - unsigned reserved1:6; - unsigned tdo_memory_size:10; - unsigned reserved0:6; + unsigned reserved0:6; + unsigned tdo_memory_size:10; + unsigned reserved1:6; + unsigned tst_prgm_memory_size:10; +#else /* Little Endian */ + unsigned tst_prgm_memory_size:10; + unsigned reserved1:6; + unsigned tdo_memory_size:10; + unsigned reserved0:6; #endif }; @@ -239,8 +233,8 @@ struct ncp_axis_mtc_MTC_INST_PARAMS0_REG_ADDR_r_t{ * */ -struct ncp_axis_mtc_MTC_SCRATCH0_REG_ADDR_r_t{ - unsigned int scratchpad0; +struct ncp_axis_mtc_MTC_SCRATCH0_REG_ADDR_r_t { + unsigned int scratchpad0; }; /*! @struct ncp_axis_mtc_MTC_SCRATCH1_REG_ADDR_r_t @@ -269,8 +263,8 @@ struct ncp_axis_mtc_MTC_SCRATCH0_REG_ADDR_r_t{ * */ -struct ncp_axis_mtc_MTC_SCRATCH1_REG_ADDR_r_t{ - unsigned int scratchpad1; +struct ncp_axis_mtc_MTC_SCRATCH1_REG_ADDR_r_t { + unsigned int scratchpad1; }; /*! @struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t @@ -396,27 +390,27 @@ struct ncp_axis_mtc_MTC_SCRATCH1_REG_ADDR_r_t{ * */ -struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t{ +struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:16; - unsigned mtc_mpu_tdo_inactive_en:1; - unsigned loop_en:1; - unsigned single_step_en:1; - unsigned start_stopn:1; - unsigned reserved1:3; - unsigned rate_sel:5; - unsigned reserved2:1; - unsigned cfg_config_ctl:3; -#else /* Little Endian */ - unsigned cfg_config_ctl:3; - unsigned reserved2:1; - unsigned rate_sel:5; - unsigned reserved1:3; - unsigned start_stopn:1; - unsigned single_step_en:1; - unsigned loop_en:1; - unsigned mtc_mpu_tdo_inactive_en:1; - unsigned reserved0:16; + unsigned reserved0:16; + unsigned mtc_mpu_tdo_inactive_en:1; + unsigned loop_en:1; + unsigned single_step_en:1; + unsigned start_stopn:1; + unsigned reserved1:3; + unsigned rate_sel:5; + unsigned reserved2:1; + unsigned cfg_config_ctl:3; +#else /* Little Endian */ + unsigned cfg_config_ctl:3; + unsigned reserved2:1; + unsigned rate_sel:5; + unsigned reserved1:3; + unsigned start_stopn:1; + unsigned single_step_en:1; + unsigned loop_en:1; + unsigned mtc_mpu_tdo_inactive_en:1; + unsigned reserved0:16; #endif }; @@ -487,19 +481,19 @@ struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t{ struct ncp_axis_mtc_MTC_CONFIG1_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:26; - unsigned record_tdo_in_shift_ir_state:1; - unsigned record_tdo_in_shift_dr_state:1; - unsigned reserved1:2; - unsigned sw_gate_tck_test_logic_reset:1; - unsigned sw_gate_tck:1; -#else /* Little Endian */ - unsigned sw_gate_tck:1; - unsigned sw_gate_tck_test_logic_reset:1; - unsigned reserved1:2; - unsigned record_tdo_in_shift_dr_state:1; - unsigned record_tdo_in_shift_ir_state:1; - unsigned reserved0:26; + unsigned reserved0:26; + unsigned record_tdo_in_shift_ir_state:1; + unsigned record_tdo_in_shift_dr_state:1; + unsigned reserved1:2; + unsigned sw_gate_tck_test_logic_reset:1; + unsigned sw_gate_tck:1; +#else /* Little Endian */ + unsigned sw_gate_tck:1; + unsigned sw_gate_tck_test_logic_reset:1; + unsigned reserved1:2; + unsigned record_tdo_in_shift_dr_state:1; + unsigned record_tdo_in_shift_ir_state:1; + unsigned reserved0:26; #endif }; @@ -554,17 +548,17 @@ struct ncp_axis_mtc_MTC_CONFIG1_REG_ADDR_r_t { * */ -struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t{ +struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:2; - unsigned tdo_record_ram_bit_counter:14; - unsigned tdo_record_ram_last_addr:8; - unsigned prgm_mem_rd_addr:8; -#else /* Little Endian */ - unsigned prgm_mem_rd_addr:8; - unsigned tdo_record_ram_last_addr:8; - unsigned tdo_record_ram_bit_counter:14; - unsigned reserved0:2; + unsigned reserved0:2; + unsigned tdo_record_ram_bit_counter:14; + unsigned tdo_record_ram_last_addr:8; + unsigned prgm_mem_rd_addr:8; +#else /* Little Endian */ + unsigned prgm_mem_rd_addr:8; + unsigned tdo_record_ram_last_addr:8; + unsigned tdo_record_ram_bit_counter:14; + unsigned reserved0:2; #endif }; @@ -749,45 +743,45 @@ struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t{ * */ -struct ncp_axis_mtc_MTC_STATUS2_REG_ADDR_r_t{ +struct ncp_axis_mtc_MTC_STATUS2_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned mtc_cmpl_enablen:1; - unsigned mtc_axm_selftst_disable:1; - unsigned reserved0:12; - unsigned nxt_task_error:1; - unsigned tst_gen_state_error:1; - unsigned reserved1:1; - unsigned pause_in_shiftir_tck_off:1; - unsigned pause_in_shiftdr_tck_off:1; - unsigned pause_in_run_test_idle_tck_off:1; - unsigned pause_in_test_logic_reset_tck_off:1; - unsigned testgen_state_machine_paused:1; - unsigned pause_in_shiftir:1; - unsigned pause_in_shiftdr:1; - unsigned curr_task_inst_i:4; - unsigned reserved2:1; - unsigned curr_task_end_of_test:1; - unsigned curr_task_pause_in_run_test_idle_state:1; - unsigned start_stopn:1; -#else /* Little Endian */ - unsigned start_stopn:1; - unsigned curr_task_pause_in_run_test_idle_state:1; - unsigned curr_task_end_of_test:1; - unsigned reserved2:1; - unsigned curr_task_inst_i:4; - unsigned pause_in_shiftdr:1; - unsigned pause_in_shiftir:1; - unsigned testgen_state_machine_paused:1; - unsigned pause_in_test_logic_reset_tck_off:1; - unsigned pause_in_run_test_idle_tck_off:1; - unsigned pause_in_shiftdr_tck_off:1; - unsigned pause_in_shiftir_tck_off:1; - unsigned reserved1:1; - unsigned tst_gen_state_error:1; - unsigned nxt_task_error:1; - unsigned reserved0:12; - unsigned mtc_axm_selftst_disable:1; - unsigned mtc_cmpl_enablen:1; + unsigned mtc_cmpl_enablen:1; + unsigned mtc_axm_selftst_disable:1; + unsigned reserved0:12; + unsigned nxt_task_error:1; + unsigned tst_gen_state_error:1; + unsigned reserved1:1; + unsigned pause_in_shiftir_tck_off:1; + unsigned pause_in_shiftdr_tck_off:1; + unsigned pause_in_run_test_idle_tck_off:1; + unsigned pause_in_test_logic_reset_tck_off:1; + unsigned testgen_state_machine_paused:1; + unsigned pause_in_shiftir:1; + unsigned pause_in_shiftdr:1; + unsigned curr_task_inst_i:4; + unsigned reserved2:1; + unsigned curr_task_end_of_test:1; + unsigned curr_task_pause_in_run_test_idle_state:1; + unsigned start_stopn:1; +#else /* Little Endian */ + unsigned start_stopn:1; + unsigned curr_task_pause_in_run_test_idle_state:1; + unsigned curr_task_end_of_test:1; + unsigned reserved2:1; + unsigned curr_task_inst_i:4; + unsigned pause_in_shiftdr:1; + unsigned pause_in_shiftir:1; + unsigned testgen_state_machine_paused:1; + unsigned pause_in_test_logic_reset_tck_off:1; + unsigned pause_in_run_test_idle_tck_off:1; + unsigned pause_in_shiftdr_tck_off:1; + unsigned pause_in_shiftir_tck_off:1; + unsigned reserved1:1; + unsigned tst_gen_state_error:1; + unsigned nxt_task_error:1; + unsigned reserved0:12; + unsigned mtc_axm_selftst_disable:1; + unsigned mtc_cmpl_enablen:1; #endif }; @@ -865,21 +859,21 @@ struct ncp_axis_mtc_MTC_STATUS2_REG_ADDR_r_t{ * */ -struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t{ +struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:27; - unsigned tdo_flush_capture_data:1; - unsigned tdo_capture_reset:1; - unsigned sw_reset:1; - unsigned cont_after_pause:1; - unsigned single_step:1; -#else /* Little Endian */ - unsigned single_step:1; - unsigned cont_after_pause:1; - unsigned sw_reset:1; - unsigned tdo_capture_reset:1; - unsigned tdo_flush_capture_data:1; - unsigned reserved0:27; + unsigned reserved0:27; + unsigned tdo_flush_capture_data:1; + unsigned tdo_capture_reset:1; + unsigned sw_reset:1; + unsigned cont_after_pause:1; + unsigned single_step:1; +#else /* Little Endian */ + unsigned single_step:1; + unsigned cont_after_pause:1; + unsigned sw_reset:1; + unsigned tdo_capture_reset:1; + unsigned tdo_flush_capture_data:1; + unsigned reserved0:27; #endif }; @@ -967,25 +961,25 @@ struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t{ * */ -struct ncp_axis_mtc_MTC_MEM_INIT_REG_ADDR_r_t{ +struct ncp_axis_mtc_MTC_MEM_INIT_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:21; - unsigned tdo_capture_mem_ini_value:1; - unsigned tdo_capture_mem_do_mem_init:1; - unsigned tdo_capture_mem_init_done:1; - unsigned reserved1:5; - unsigned tst_prgm_mem_ini_value:1; - unsigned tst_prgm_mem_do_mem_init:1; - unsigned tst_prgm_mem_init_done:1; -#else /* Little Endian */ - unsigned tst_prgm_mem_init_done:1; - unsigned tst_prgm_mem_do_mem_init:1; - unsigned tst_prgm_mem_ini_value:1; - unsigned reserved1:5; - unsigned tdo_capture_mem_init_done:1; - unsigned tdo_capture_mem_do_mem_init:1; - unsigned tdo_capture_mem_ini_value:1; - unsigned reserved0:21; + unsigned reserved0:21; + unsigned tdo_capture_mem_ini_value:1; + unsigned tdo_capture_mem_do_mem_init:1; + unsigned tdo_capture_mem_init_done:1; + unsigned reserved1:5; + unsigned tst_prgm_mem_ini_value:1; + unsigned tst_prgm_mem_do_mem_init:1; + unsigned tst_prgm_mem_init_done:1; +#else /* Little Endian */ + unsigned tst_prgm_mem_init_done:1; + unsigned tst_prgm_mem_do_mem_init:1; + unsigned tst_prgm_mem_ini_value:1; + unsigned reserved1:5; + unsigned tdo_capture_mem_init_done:1; + unsigned tdo_capture_mem_do_mem_init:1; + unsigned tdo_capture_mem_ini_value:1; + unsigned reserved0:21; #endif }; @@ -1031,18 +1025,18 @@ struct ncp_axis_mtc_MTC_MEM_INIT_REG_ADDR_r_t{ * */ -struct ncp_axis_mtc_MTC_ECC_DISABLE_REG_ADDR_r_t{ +struct ncp_axis_mtc_MTC_ECC_DISABLE_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:30; - unsigned disable_ecc_mtc_tst_prgm_mem:1; - unsigned disable_ecc_mtc_tdo_record_mem:1; -#else /* Little Endian */ - unsigned disable_ecc_mtc_tdo_record_mem:1; - unsigned disable_ecc_mtc_tst_prgm_mem:1; - unsigned reserved0:30; + unsigned reserved0:30; + unsigned disable_ecc_mtc_tst_prgm_mem:1; + unsigned disable_ecc_mtc_tdo_record_mem:1; +#else /* Little Endian */ + unsigned disable_ecc_mtc_tdo_record_mem:1; + unsigned disable_ecc_mtc_tst_prgm_mem:1; + unsigned reserved0:30; #endif -} ; +}; /*! @struct ncp_axis_mtc_MTC_ECC_INVERT_EN_REG_ADDR_r_t * @brief MTC MEM Invert Enable ECC Register @@ -1082,15 +1076,15 @@ struct ncp_axis_mtc_MTC_ECC_DISABLE_REG_ADDR_r_t{ * */ -struct ncp_axis_mtc_MTC_ECC_INVERT_EN_REG_ADDR_r_t{ +struct ncp_axis_mtc_MTC_ECC_INVERT_EN_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:30; - unsigned ecc_invert_en_mtc_tst_prgm_mem:1; - unsigned ecc_invert_en_tc_tdo_record_mem:1; -#else /* Little Endian */ - unsigned ecc_invert_en_tc_tdo_record_mem:1; - unsigned ecc_invert_en_mtc_tst_prgm_mem:1; - unsigned reserved0:30; + unsigned reserved0:30; + unsigned ecc_invert_en_mtc_tst_prgm_mem:1; + unsigned ecc_invert_en_tc_tdo_record_mem:1; +#else /* Little Endian */ + unsigned ecc_invert_en_tc_tdo_record_mem:1; + unsigned ecc_invert_en_mtc_tst_prgm_mem:1; + unsigned reserved0:30; #endif }; @@ -1132,11 +1126,11 @@ struct ncp_axis_mtc_MTC_ECC_INVERT_EN_REG_ADDR_r_t{ struct ncp_axis_mtc_MTC_ECC_INVERT_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:25; - unsigned ecc_invert_reg:7; -#else /* Little Endian */ - unsigned ecc_invert_reg:7; - unsigned reserved0:25; + unsigned reserved0:25; + unsigned ecc_invert_reg:7; +#else /* Little Endian */ + unsigned ecc_invert_reg:7; + unsigned reserved0:25; #endif }; @@ -1244,31 +1238,31 @@ struct ncp_axis_mtc_MTC_ECC_INVERT_REG_ADDR_r_t { struct ncp_axis_mtc_MTC_DEBUG0_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned mtc_testgen_tdo_inactive_enb:1; - unsigned curr_task_gap_tck_en:1; - unsigned curr_task_tck_ctl_i:1; - unsigned curr_task_end_state_ctl_i:1; - unsigned reserved0:2; - unsigned curr_task_ctl_i:2; - unsigned reserved1:3; - unsigned nxt_tstgen_tdi_cnt30:5; - unsigned reserved2:4; - unsigned task_sub_state:4; - unsigned reserved3:4; - unsigned nxt_task_inst_i:4; -#else /* Little Endian */ - unsigned nxt_task_inst_i:4; - unsigned reserved3:4; - unsigned task_sub_state:4; - unsigned reserved2:4; - unsigned nxt_tstgen_tdi_cnt30:5; - unsigned reserved1:3; - unsigned curr_task_ctl_i:2; - unsigned reserved0:2; - unsigned curr_task_end_state_ctl_i:1; - unsigned curr_task_tck_ctl_i:1; - unsigned curr_task_gap_tck_en:1; - unsigned mtc_testgen_tdo_inactive_enb:1; + unsigned mtc_testgen_tdo_inactive_enb:1; + unsigned curr_task_gap_tck_en:1; + unsigned curr_task_tck_ctl_i:1; + unsigned curr_task_end_state_ctl_i:1; + unsigned reserved0:2; + unsigned curr_task_ctl_i:2; + unsigned reserved1:3; + unsigned nxt_tstgen_tdi_cnt30:5; + unsigned reserved2:4; + unsigned task_sub_state:4; + unsigned reserved3:4; + unsigned nxt_task_inst_i:4; +#else /* Little Endian */ + unsigned nxt_task_inst_i:4; + unsigned reserved3:4; + unsigned task_sub_state:4; + unsigned reserved2:4; + unsigned nxt_tstgen_tdi_cnt30:5; + unsigned reserved1:3; + unsigned curr_task_ctl_i:2; + unsigned reserved0:2; + unsigned curr_task_end_state_ctl_i:1; + unsigned curr_task_tck_ctl_i:1; + unsigned curr_task_gap_tck_en:1; + unsigned mtc_testgen_tdo_inactive_enb:1; #endif }; @@ -1441,50 +1435,50 @@ struct ncp_axis_mtc_MTC_DEBUG0_REG_ADDR_r_t { struct ncp_axis_mtc_MTC_DEBUG1_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned curr_task_no_operation:1; - unsigned curr_task_test_reset_1:1; - unsigned curr_task_test_reset_2:1; - unsigned curr_task_load_jtag_inst_reg:1; - unsigned curr_task_load_jtag_data_reg:1; - unsigned curr_task_mtc_reserved_task_id_5:1; - unsigned curr_task_mtc_reserved_task_id_6:1; - unsigned curr_task_wait_in_run_test_idle_state_xtck_cycles:1; - unsigned curr_task_pause_in_run_test_idle_state:1; - unsigned curr_task_end_of_test:1; - unsigned curr_task_load_jtag_data_reg_and_pause_in_pause_dr:1; - unsigned curr_task_load_jtag_data_reg_continue_from_pause_dr:1; - unsigned - curr_task_load_jtag_data_reg_continue_from_pause_dr_and_stop_in_pause_dr : 1; - unsigned curr_task_load_jtag_inst_reg_and_pause_in_pause_ir:1; - unsigned curr_task_load_jtag_inst_reg_continue_from_pause_ir:1; - unsigned - curr_task_load_jtag_inst_reg_continue_from_pause_ir_and_stop_in_pause_ir : 1; - unsigned reserved0:4; - unsigned curr_task_inst_i:4; - unsigned prgm_mem_rd_addr:8; -#else /* Little Endian */ - unsigned prgm_mem_rd_addr:8; - unsigned curr_task_inst_i:4; - unsigned reserved0:4; - unsigned - curr_task_load_jtag_inst_reg_continue_from_pause_ir_and_stop_in_pause_ir : 1; - unsigned curr_task_load_jtag_inst_reg_continue_from_pause_ir:1; - unsigned curr_task_load_jtag_inst_reg_and_pause_in_pause_ir:1; - unsigned - curr_task_load_jtag_data_reg_continue_from_pause_dr_and_stop_in_pause_dr : 1; - unsigned - curr_task_load_jtag_data_reg_continue_from_pause_dr : 1; - unsigned curr_task_load_jtag_data_reg_and_pause_in_pause_dr:1; - unsigned curr_task_end_of_test:1; - unsigned curr_task_pause_in_run_test_idle_state:1; - unsigned curr_task_wait_in_run_test_idle_state_xtck_cycles:1; - unsigned curr_task_mtc_reserved_task_id_6:1; - unsigned curr_task_mtc_reserved_task_id_5:1; - unsigned curr_task_load_jtag_data_reg:1; - unsigned curr_task_load_jtag_inst_reg:1; - unsigned curr_task_test_reset_2:1; - unsigned curr_task_test_reset_1:1; - unsigned curr_task_no_operation:1; + unsigned curr_task_no_operation:1; + unsigned curr_task_test_reset_1:1; + unsigned curr_task_test_reset_2:1; + unsigned curr_task_load_jtag_inst_reg:1; + unsigned curr_task_load_jtag_data_reg:1; + unsigned curr_task_mtc_reserved_task_id_5:1; + unsigned curr_task_mtc_reserved_task_id_6:1; + unsigned curr_task_wait_in_run_test_idle_state_xtck_cycles:1; + unsigned curr_task_pause_in_run_test_idle_state:1; + unsigned curr_task_end_of_test:1; + unsigned curr_task_load_jtag_data_reg_and_pause_in_pause_dr:1; + unsigned curr_task_load_jtag_data_reg_continue_from_pause_dr:1; + unsigned + curr_task_load_jtag_data_reg_continue_from_pause_dr_and_stop_in_pause_dr:1; + unsigned curr_task_load_jtag_inst_reg_and_pause_in_pause_ir:1; + unsigned curr_task_load_jtag_inst_reg_continue_from_pause_ir:1; + unsigned + curr_task_load_jtag_inst_reg_continue_from_pause_ir_and_stop_in_pause_ir:1; + unsigned reserved0:4; + unsigned curr_task_inst_i:4; + unsigned prgm_mem_rd_addr:8; +#else /* Little Endian */ + unsigned prgm_mem_rd_addr:8; + unsigned curr_task_inst_i:4; + unsigned reserved0:4; + unsigned + curr_task_load_jtag_inst_reg_continue_from_pause_ir_and_stop_in_pause_ir:1; + unsigned curr_task_load_jtag_inst_reg_continue_from_pause_ir:1; + unsigned curr_task_load_jtag_inst_reg_and_pause_in_pause_ir:1; + unsigned + curr_task_load_jtag_data_reg_continue_from_pause_dr_and_stop_in_pause_dr:1; + unsigned + curr_task_load_jtag_data_reg_continue_from_pause_dr:1; + unsigned curr_task_load_jtag_data_reg_and_pause_in_pause_dr:1; + unsigned curr_task_end_of_test:1; + unsigned curr_task_pause_in_run_test_idle_state:1; + unsigned curr_task_wait_in_run_test_idle_state_xtck_cycles:1; + unsigned curr_task_mtc_reserved_task_id_6:1; + unsigned curr_task_mtc_reserved_task_id_5:1; + unsigned curr_task_load_jtag_data_reg:1; + unsigned curr_task_load_jtag_inst_reg:1; + unsigned curr_task_test_reset_2:1; + unsigned curr_task_test_reset_1:1; + unsigned curr_task_no_operation:1; #endif }; @@ -1616,45 +1610,45 @@ struct ncp_axis_mtc_MTC_DEBUG1_REG_ADDR_r_t { * */ -struct ncp_axis_mtc_MTC_DEBUG2_REG_ADDR_r_t{ +struct ncp_axis_mtc_MTC_DEBUG2_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned curr_tapc_update_ir:1; - unsigned curr_tapc_exit2_ir:1; - unsigned curr_tapc_pause_ir:1; - unsigned curr_tapc_exit1_ir:1; - unsigned curr_tapc_shift_ir:1; - unsigned curr_tapc_capture_ir:1; - unsigned curr_tapc_update_dr:1; - unsigned curr_tapc_exit2_dr:1; - unsigned curr_tapc_pause_dr:1; - unsigned curr_tapc_exit1_dr:1; - unsigned curr_tapc_shift_dr:1; - unsigned curr_tapc_capture_dr:1; - unsigned curr_tapc_select_ir_scan:1; - unsigned curr_tapc_select_dr_scan:1; - unsigned curr_tapc_run_test_idle:1; - unsigned curr_tapc_test_logic_reset:1; - unsigned reserved0:12; - unsigned tapc_state:4; -#else /* Little Endian */ - unsigned tapc_state:4; - unsigned reserved0:12; - unsigned curr_tapc_test_logic_reset:1; - unsigned curr_tapc_run_test_idle:1; - unsigned curr_tapc_select_dr_scan:1; - unsigned curr_tapc_select_ir_scan:1; - unsigned curr_tapc_capture_dr:1; - unsigned curr_tapc_shift_dr:1; - unsigned curr_tapc_exit1_dr:1; - unsigned curr_tapc_pause_dr:1; - unsigned curr_tapc_exit2_dr:1; - unsigned curr_tapc_update_dr:1; - unsigned curr_tapc_capture_ir:1; - unsigned curr_tapc_shift_ir:1; - unsigned curr_tapc_exit1_ir:1; - unsigned curr_tapc_pause_ir:1; - unsigned curr_tapc_exit2_ir:1; - unsigned curr_tapc_update_ir:1; + unsigned curr_tapc_update_ir:1; + unsigned curr_tapc_exit2_ir:1; + unsigned curr_tapc_pause_ir:1; + unsigned curr_tapc_exit1_ir:1; + unsigned curr_tapc_shift_ir:1; + unsigned curr_tapc_capture_ir:1; + unsigned curr_tapc_update_dr:1; + unsigned curr_tapc_exit2_dr:1; + unsigned curr_tapc_pause_dr:1; + unsigned curr_tapc_exit1_dr:1; + unsigned curr_tapc_shift_dr:1; + unsigned curr_tapc_capture_dr:1; + unsigned curr_tapc_select_ir_scan:1; + unsigned curr_tapc_select_dr_scan:1; + unsigned curr_tapc_run_test_idle:1; + unsigned curr_tapc_test_logic_reset:1; + unsigned reserved0:12; + unsigned tapc_state:4; +#else /* Little Endian */ + unsigned tapc_state:4; + unsigned reserved0:12; + unsigned curr_tapc_test_logic_reset:1; + unsigned curr_tapc_run_test_idle:1; + unsigned curr_tapc_select_dr_scan:1; + unsigned curr_tapc_select_ir_scan:1; + unsigned curr_tapc_capture_dr:1; + unsigned curr_tapc_shift_dr:1; + unsigned curr_tapc_exit1_dr:1; + unsigned curr_tapc_pause_dr:1; + unsigned curr_tapc_exit2_dr:1; + unsigned curr_tapc_update_dr:1; + unsigned curr_tapc_capture_ir:1; + unsigned curr_tapc_shift_ir:1; + unsigned curr_tapc_exit1_ir:1; + unsigned curr_tapc_pause_ir:1; + unsigned curr_tapc_exit2_ir:1; + unsigned curr_tapc_update_ir:1; #endif }; @@ -1700,13 +1694,13 @@ struct ncp_axis_mtc_MTC_DEBUG2_REG_ADDR_r_t{ struct ncp_axis_mtc_MTC_DEBUG3_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned nxt_tdi_shift_data_d:1; - unsigned reserved0:1; - unsigned nxt_tdi_shift_data:30; -#else /* Little Endian */ - unsigned nxt_tdi_shift_data:30; - unsigned reserved0:1; - unsigned nxt_tdi_shift_data_d:1; + unsigned nxt_tdi_shift_data_d:1; + unsigned reserved0:1; + unsigned nxt_tdi_shift_data:30; +#else /* Little Endian */ + unsigned nxt_tdi_shift_data:30; + unsigned reserved0:1; + unsigned nxt_tdi_shift_data_d:1; #endif }; @@ -1736,9 +1730,9 @@ struct ncp_axis_mtc_MTC_DEBUG3_REG_ADDR_r_t { * */ -struct ncp_axis_mtc_MTC_DEBUG4_REG_ADDR_r_t{ - unsigned int nxt_task_inst_i; -} ; +struct ncp_axis_mtc_MTC_DEBUG4_REG_ADDR_r_t { + unsigned int nxt_task_inst_i; +}; /*! @struct ncp_axis_mtc_MTC_DEBUG5_REG_ADDR_r_t * @brief MTC Debug5 Register @@ -1774,13 +1768,13 @@ struct ncp_axis_mtc_MTC_DEBUG4_REG_ADDR_r_t{ struct ncp_axis_mtc_MTC_DEBUG5_REG_ADDR_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:6; - unsigned delay_shift_cnt:26; -#else /* Little Endian */ - unsigned delay_shift_cnt:26; - unsigned reserved0:6; + unsigned reserved0:6; + unsigned delay_shift_cnt:26; +#else /* Little Endian */ + unsigned delay_shift_cnt:26; + unsigned reserved0:6; #endif -} ; +}; /*! @struct ncp_axis_mtc_MTC_PRGM_MEM_START_ADDR_r_t * @brief MTC Test Program Memory @@ -1841,8 +1835,8 @@ struct ncp_axis_mtc_MTC_DEBUG5_REG_ADDR_r_t { * */ -struct ncp_axis_mtc_MTC_PRGM_MEM_START_ADDR_r_t { - unsigned int tst_prgm; +struct ncp_axis_mtc_MTC_PRGM_MEM_START_ADDR_r_t { + unsigned int tst_prgm; }; /*! @struct ncp_axis_mtc_MTC_TDO_CAPTURE_MEM_START_ADDR_r_t @@ -1875,7 +1869,7 @@ struct ncp_axis_mtc_MTC_PRGM_MEM_START_ADDR_r_t { struct ncp_axis_mtc_MTC_TDO_CAPTURE_MEM_START_ADDR_r_t { - unsigned int tdo_capture; + unsigned int tdo_capture; }; /*! @struct ncp_axis_mtc_mtc_tstgen_int_status_r_t @@ -1960,25 +1954,25 @@ struct ncp_axis_mtc_MTC_TDO_CAPTURE_MEM_START_ADDR_r_t { * */ -struct ncp_axis_mtc_mtc_tstgen_int_status_r_t{ +struct ncp_axis_mtc_mtc_tstgen_int_status_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:25; - unsigned tdo_record_ram_addr_overflow_os:1; - unsigned nxt_task_error_os:1; - unsigned tst_gen_state_error_os:1; - unsigned cont_after_pause_os:1; - unsigned pause_in_shiftir_os:1; - unsigned pause_in_shiftdr_os:1; - unsigned curr_task_end_of_test_os:1; -#else /* Little Endian */ - unsigned curr_task_end_of_test_os:1; - unsigned pause_in_shiftdr_os:1; - unsigned pause_in_shiftir_os:1; - unsigned cont_after_pause_os:1; - unsigned tst_gen_state_error_os:1; - unsigned nxt_task_error_os:1; - unsigned tdo_record_ram_addr_overflow_os:1; - unsigned reserved0:25; + unsigned reserved0:25; + unsigned tdo_record_ram_addr_overflow_os:1; + unsigned nxt_task_error_os:1; + unsigned tst_gen_state_error_os:1; + unsigned cont_after_pause_os:1; + unsigned pause_in_shiftir_os:1; + unsigned pause_in_shiftdr_os:1; + unsigned curr_task_end_of_test_os:1; +#else /* Little Endian */ + unsigned curr_task_end_of_test_os:1; + unsigned pause_in_shiftdr_os:1; + unsigned pause_in_shiftir_os:1; + unsigned cont_after_pause_os:1; + unsigned tst_gen_state_error_os:1; + unsigned nxt_task_error_os:1; + unsigned tdo_record_ram_addr_overflow_os:1; + unsigned reserved0:25; #endif }; @@ -2064,27 +2058,27 @@ struct ncp_axis_mtc_mtc_tstgen_int_status_r_t{ * */ -struct ncp_axis_mtc_mtc_tstgen_int_en_r_t{ +struct ncp_axis_mtc_mtc_tstgen_int_en_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:25; - unsigned tdo_record_ram_addr_overflow_os:1; - unsigned nxt_task_error_os:1; - unsigned tst_gen_state_error_os:1; - unsigned cont_after_pause_os:1; - unsigned pause_in_shiftir_os:1; - unsigned pause_in_shiftdr_os:1; - unsigned curr_task_end_of_test_os:1; -#else /* Little Endian */ - unsigned curr_task_end_of_test_os:1; - unsigned pause_in_shiftdr_os:1; - unsigned pause_in_shiftir_os:1; - unsigned cont_after_pause_os:1; - unsigned tst_gen_state_error_os:1; - unsigned nxt_task_error_os:1; - unsigned tdo_record_ram_addr_overflow_os:1; - unsigned reserved0:25; + unsigned reserved0:25; + unsigned tdo_record_ram_addr_overflow_os:1; + unsigned nxt_task_error_os:1; + unsigned tst_gen_state_error_os:1; + unsigned cont_after_pause_os:1; + unsigned pause_in_shiftir_os:1; + unsigned pause_in_shiftdr_os:1; + unsigned curr_task_end_of_test_os:1; +#else /* Little Endian */ + unsigned curr_task_end_of_test_os:1; + unsigned pause_in_shiftdr_os:1; + unsigned pause_in_shiftir_os:1; + unsigned cont_after_pause_os:1; + unsigned tst_gen_state_error_os:1; + unsigned nxt_task_error_os:1; + unsigned tdo_record_ram_addr_overflow_os:1; + unsigned reserved0:25; #endif -} ; +}; /*! @struct ncp_axis_mtc_mtc_tstgen_int_force_r_t * @brief Interrupt Force Register @@ -2172,25 +2166,25 @@ struct ncp_axis_mtc_mtc_tstgen_int_en_r_t{ * */ -struct ncp_axis_mtc_mtc_tstgen_int_force_r_t{ +struct ncp_axis_mtc_mtc_tstgen_int_force_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:25; - unsigned tdo_record_ram_addr_overflow_os:1; - unsigned nxt_task_error_os:1; - unsigned tst_gen_state_error_os:1; - unsigned cont_after_pause_os:1; - unsigned pause_in_shiftir_os:1; - unsigned pause_in_shiftdr_os:1; - unsigned curr_task_end_of_test_os:1; -#else /* Little Endian */ - unsigned curr_task_end_of_test_os:1; - unsigned pause_in_shiftdr_os:1; - unsigned pause_in_shiftir_os:1; - unsigned cont_after_pause_os:1; - unsigned tst_gen_state_error_os:1; - unsigned nxt_task_error_os:1; - unsigned tdo_record_ram_addr_overflow_os:1; - unsigned reserved0:25; + unsigned reserved0:25; + unsigned tdo_record_ram_addr_overflow_os:1; + unsigned nxt_task_error_os:1; + unsigned tst_gen_state_error_os:1; + unsigned cont_after_pause_os:1; + unsigned pause_in_shiftir_os:1; + unsigned pause_in_shiftdr_os:1; + unsigned curr_task_end_of_test_os:1; +#else /* Little Endian */ + unsigned curr_task_end_of_test_os:1; + unsigned pause_in_shiftdr_os:1; + unsigned pause_in_shiftir_os:1; + unsigned cont_after_pause_os:1; + unsigned tst_gen_state_error_os:1; + unsigned nxt_task_error_os:1; + unsigned tdo_record_ram_addr_overflow_os:1; + unsigned reserved0:25; #endif }; @@ -2244,20 +2238,20 @@ struct ncp_axis_mtc_mtc_tstgen_int_force_r_t{ * */ -struct ncp_axis_mtc_mtc_ecc_int_status_r_t{ +struct ncp_axis_mtc_mtc_ecc_int_status_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:28; - unsigned ecc_mult_tstgen_prgm_mem_os:1; - unsigned ecc_mult_tdo_capture_mem_os:1; - unsigned ecc_single_tstgen_prgm_mem_os:1; - unsigned ecc_single_tdo_capture_mem_os:1; -#else /* Little Endian */ - unsigned ecc_single_tdo_capture_mem_os:1; - unsigned ecc_single_tstgen_prgm_mem_os:1; - unsigned ecc_mult_tdo_capture_mem_os:1; - unsigned ecc_mult_tstgen_prgm_mem_os:1; - unsigned reserved0:28; + unsigned reserved0:28; + unsigned ecc_mult_tstgen_prgm_mem_os:1; + unsigned ecc_mult_tdo_capture_mem_os:1; + unsigned ecc_single_tstgen_prgm_mem_os:1; + unsigned ecc_single_tdo_capture_mem_os:1; +#else /* Little Endian */ + unsigned ecc_single_tdo_capture_mem_os:1; + unsigned ecc_single_tstgen_prgm_mem_os:1; + unsigned ecc_mult_tdo_capture_mem_os:1; + unsigned ecc_mult_tstgen_prgm_mem_os:1; + unsigned reserved0:28; #endif }; @@ -2313,17 +2307,17 @@ struct ncp_axis_mtc_mtc_ecc_int_status_r_t{ struct ncp_axis_mtc_mtc_ecc_int_en_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:28; - unsigned ecc_mult_tstgen_prgm_mem_os:1; - unsigned ecc_mult_tdo_capture_mem_os:1; - unsigned ecc_single_tstgen_prgm_mem_os:1; - unsigned ecc_single_tdo_capture_mem_os:1; -#else /* Little Endian */ - unsigned ecc_single_tdo_capture_mem_os:1; - unsigned ecc_single_tstgen_prgm_mem_os:1; - unsigned ecc_mult_tdo_capture_mem_os:1; - unsigned ecc_mult_tstgen_prgm_mem_os:1; - unsigned reserved0:28; + unsigned reserved0:28; + unsigned ecc_mult_tstgen_prgm_mem_os:1; + unsigned ecc_mult_tdo_capture_mem_os:1; + unsigned ecc_single_tstgen_prgm_mem_os:1; + unsigned ecc_single_tdo_capture_mem_os:1; +#else /* Little Endian */ + unsigned ecc_single_tdo_capture_mem_os:1; + unsigned ecc_single_tstgen_prgm_mem_os:1; + unsigned ecc_mult_tdo_capture_mem_os:1; + unsigned ecc_mult_tstgen_prgm_mem_os:1; + unsigned reserved0:28; #endif }; @@ -2381,44 +2375,40 @@ struct ncp_axis_mtc_mtc_ecc_int_en_r_t { * */ -struct ncp_axis_mtc_mtc_ecc_int_force_r_t{ +struct ncp_axis_mtc_mtc_ecc_int_force_r_t { #ifdef NCP_BIG_ENDIAN - unsigned reserved0:28; - unsigned ecc_mult_tstgen_prgm_mem_os:1; - unsigned ecc_mult_tdo_capture_mem_os:1; - unsigned ecc_single_tstgen_prgm_mem_os:1; - unsigned ecc_single_tdo_capture_mem_os:1; -#else /* Little Endian */ - unsigned ecc_single_tdo_capture_mem_os:1; - unsigned ecc_single_tstgen_prgm_mem_os:1; - unsigned ecc_mult_tdo_capture_mem_os:1; - unsigned ecc_mult_tstgen_prgm_mem_os:1; - unsigned reserved0:28; + unsigned reserved0:28; + unsigned ecc_mult_tstgen_prgm_mem_os:1; + unsigned ecc_mult_tdo_capture_mem_os:1; + unsigned ecc_single_tstgen_prgm_mem_os:1; + unsigned ecc_single_tdo_capture_mem_os:1; +#else /* Little Endian */ + unsigned ecc_single_tdo_capture_mem_os:1; + unsigned ecc_single_tstgen_prgm_mem_os:1; + unsigned ecc_mult_tdo_capture_mem_os:1; + unsigned ecc_mult_tstgen_prgm_mem_os:1; + unsigned reserved0:28; #endif }; - /******************************************************/ /* end of RDL register definitions */ /******************************************************/ - struct mtc_device { - struct kref ref; - struct platform_device *pdev; - unsigned long flags; -#define FLAG_REGISTERED 0 /* Misc device registered */ + struct kref ref; + struct platform_device *pdev; + unsigned long flags; +#define FLAG_REGISTERED 0 /* Misc device registered */ struct mtc_regs __iomem *regs; - u32 __iomem *prgmem; - u32 __iomem *tdomem; - unsigned int irq; - struct miscdevice char_device; + u32 __iomem *prgmem; + u32 __iomem *tdomem; + unsigned int irq; + struct miscdevice char_device; }; #define miscdev_to_mtc(mdev) container_of(mdev, struct mtc_device, char_device) - - /* Called when removed and last reference is released */ static void mtc_destroy(struct kref *ref); @@ -2427,11 +2417,10 @@ static void mtc_destroy(struct kref *ref); * * Returns 0 for success or negative errno. */ -static int -mtc_dev_open(struct inode *inode, struct file *filp) +static int mtc_dev_open(struct inode *inode, struct file *filp) { struct miscdevice *misc = filp->private_data; - struct mtc_device *dev = miscdev_to_mtc(misc); + struct mtc_device *dev = miscdev_to_mtc(misc); pr_debug("mtc_dev_open(%p)\n", dev); kref_get(&dev->ref); return 0; @@ -2440,11 +2429,10 @@ mtc_dev_open(struct inode *inode, struct file *filp) /** * mtc_dev_release */ -static int -mtc_dev_release(struct inode *inode, struct file *filp) +static int mtc_dev_release(struct inode *inode, struct file *filp) { struct miscdevice *misc = filp->private_data; - struct mtc_device *dev = miscdev_to_mtc(misc); + struct mtc_device *dev = miscdev_to_mtc(misc); pr_debug("mtc_dev_release(%p)\n", dev); kref_put(&dev->ref, mtc_destroy); return 0; @@ -2456,17 +2444,14 @@ mtc_dev_release(struct inode *inode, struct file *filp) * Returns number of valid bits read or negative errno. */ static ssize_t -mtc_dev_read(struct file *filp, - char __user *data, - size_t len, - loff_t *ppose) +mtc_dev_read(struct file *filp, char __user *data, size_t len, loff_t *ppose) { struct miscdevice *misc = filp->private_data; - struct mtc_device *dev = miscdev_to_mtc(misc); - u32 __iomem *ptdo; - u32 tdo_size_word, tdo_size_bit; /* data to be read in words */ - struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t status1Reg = {0}; - struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t exec1Reg = {0}; + struct mtc_device *dev = miscdev_to_mtc(misc); + u32 __iomem *ptdo; + u32 tdo_size_word, tdo_size_bit; /* data to be read in words */ + struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t status1Reg = { 0 }; + struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t exec1Reg = { 0 }; pr_debug("mtc_dev_read(%u @ %llu)\n", len, *ppose); ptdo = dev->tdomem; @@ -2477,21 +2462,22 @@ mtc_dev_read(struct file *filp, /* read status 1register */ status1Reg = - *((struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t *) &(dev->regs->status1)); + *((struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t *) + &(dev->regs->status1)); tdo_size_bit = status1Reg.tdo_record_ram_bit_counter; /* test code for mtc memory sim only */ - /* tdo_size_bit = 8192;*/ + /* tdo_size_bit = 8192; */ /* end of test code */ - tdo_size_word = (tdo_size_bit + 31)/32; - #ifdef DEBUG - printk(KERN_DEBUG"mtc_dev_read(), tdo_bit=%d tdo_word=%d \n", - tdo_size_bit, tdo_size_word); - #endif + tdo_size_word = (tdo_size_bit + 31) / 32; +#ifdef DEBUG + printk(KERN_DEBUG "mtc_dev_read(), tdo_bit=%d tdo_word=%d\n", + tdo_size_bit, tdo_size_word); +#endif /* copy tdo data to user space, always read from location 0 - because we reset tdomem after each read */ - if (copy_to_user(data, ptdo, tdo_size_word*4)) + because we reset tdomem after each read */ + if (copy_to_user(data, ptdo, tdo_size_word * 4)) return -EFAULT; /* data sent to user, reset tdo capture buffer */ @@ -2511,40 +2497,39 @@ mtc_dev_read(struct file *filp, static ssize_t mtc_dev_write(struct file *filp, - const char __user *data, - size_t len, - loff_t *ppose) + const char __user *data, size_t len, loff_t *ppose) { struct miscdevice *misc = filp->private_data; - struct mtc_device *dev = miscdev_to_mtc(misc); - u32 __iomem *pprg; - u32 mtc_buf[256]; /* max 256 words */ - u32 size, size1, isWraparound = 0, i; /* size in word */ - struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t status1Reg = {0}; + struct mtc_device *dev = miscdev_to_mtc(misc); + u32 __iomem *pprg; + u32 mtc_buf[256]; /* max 256 words */ + u32 size, size1, isWraparound = 0, i; /* size in word */ + struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t status1Reg = { 0 }; pr_debug("mtc_dev_write(%u @ %llu)\n", len, *ppose); if (len > 1024) return -EINVAL; - size = len/4; + size = len / 4; size1 = size; /* copy to a lcoal buffer */ memset(mtc_buf, 0, 1024); - if (copy_from_user((void *)mtc_buf, (void *) data, len)) { + if (copy_from_user((void *)mtc_buf, (void *)data, len)) { pr_debug("MTC Error write\n"); return -EFAULT; } /* read status 1register, find the starting write offset */ status1Reg = - *((struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t *) &(dev->regs->status1)); + *((struct ncp_axis_mtc_MTC_STATUS1_REG_ADDR_r_t *) + &(dev->regs->status1)); - /* TEST CODE when mtc sim is used*/ - /* status1Reg.prgm_mem_rd_addr = 253;*/ - /* printk(KERN_DEBUG"buf offset=%d\n",status1Reg.prgm_mem_rd_addr );*/ + /* TEST CODE when mtc sim is used */ + /* status1Reg.prgm_mem_rd_addr = 253; */ + /* printk(KERN_DEBUG"buf offset=%d\n",status1Reg.prgm_mem_rd_addr ); */ /*END OF TEST CODE */ /* find starting location of the write */ @@ -2556,35 +2541,39 @@ mtc_dev_write(struct file *filp, /* number of words load from starting location */ size1 = 256 - status1Reg.prgm_mem_rd_addr; /*number of words load from location 0 will be size-size1 */ - #ifdef DEBUG - printk(KERN_DEBUG"Wraparound size=%d, size1=%d size-size1=%d\n", - size, size1, size-size1); - #endif - } - #ifdef DEBUG - printk(KERN_DEBUG"Appending buff size1=%d\n", size1); - #endif +#ifdef DEBUG + printk(KERN_DEBUG + "Wraparound size=%d, size1=%d size-size1=%d\n", size, + size1, size - size1); +#endif + } +#ifdef DEBUG + printk(KERN_DEBUG "Appending buff size1=%d\n", size1); +#endif + for (i = 0; i < size1; i++) { - #ifdef DEBUG - printk(KERN_DEBUG"i=%d mtc_buf[i]=%d pprg=0x%x\n", - i, mtc_buf[i], (u32) pprg); - #endif - *pprg = mtc_buf[i]; +#ifdef DEBUG + printk(KERN_DEBUG "i=%d mtc_buf[i]=%d pprg=0x%x\n", + i, mtc_buf[i], (u32) pprg); +#endif + *pprg = mtc_buf[i]; pprg++; - } + } /* wraparound, copy the 2nd half */ if (isWraparound) { - pprg = dev->prgmem; /* reset write pointer to location 0 */ - #ifdef DEBUG - printk(KERN_DEBUG"\n\nWraparound buff size=%d\n", size-size1); - #endif - for (i = 0; i < (size-size1); i++) { - #ifdef DEBUG - printk(KERN_DEBUG"i=%d mtc_buf[size1+i]=%d pprg=0x%x\n", - i, mtc_buf[size1+i], (u32) pprg); - #endif - *pprg = mtc_buf[size1+i]; + pprg = dev->prgmem; /* reset write pointer to location 0 */ +#ifdef DEBUG + printk(KERN_DEBUG "\n\nWraparound buff size=%d\n", + size - size1); +#endif + for (i = 0; i < (size - size1); i++) { +#ifdef DEBUG + printk(KERN_DEBUG + "i=%d mtc_buf[size1+i]=%d pprg=0x%x\n", i, + mtc_buf[size1 + i], (u32) pprg); +#endif + *pprg = mtc_buf[size1 + i]; pprg++; } } @@ -2597,15 +2586,13 @@ mtc_dev_write(struct file *filp, * */ -static long _mtc_config(struct mtc_device *dev, - struct lsi_mtc_cfg_t *pMTCCfg); - +static long _mtc_config(struct mtc_device *dev, struct lsi_mtc_cfg_t *pMTCCfg); static long mtc_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { struct miscdevice *misc = filp->private_data; - struct mtc_device *dev = miscdev_to_mtc(misc); + struct mtc_device *dev = miscdev_to_mtc(misc); long ret = 0; u32 addr, tmp2; unsigned long numByteCopied; @@ -2615,197 +2602,215 @@ mtc_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) switch (cmd) { case MTC_DEBUG_OP: - numByteCopied = - copy_from_user((void *) &addr, (void *) arg, sizeof(unsigned int)); - if (numByteCopied) { - printk(KERN_DEBUG"MTC Error ioctl\n"); - return -EFAULT; - } - tmp2 = *((u32 *)dev->regs + addr/4); + numByteCopied = + copy_from_user((void *)&addr, (void *)arg, + sizeof(unsigned int)); + if (numByteCopied) { + printk(KERN_DEBUG "MTC Error ioctl\n"); + return -EFAULT; + } + tmp2 = *((u32 *) dev->regs + addr / 4); - if (copy_to_user((void *)arg, &tmp2, sizeof(unsigned int))) - return -EFAULT; + if (copy_to_user((void *)arg, &tmp2, sizeof(unsigned int))) + return -EFAULT; - break; + break; case MTC_CFG: - { - struct lsi_mtc_cfg_t mtc_cfg; - if (copy_from_user((void *) &mtc_cfg, (void *) arg, sizeof(mtc_cfg))) { - printk(KERN_DEBUG"MTC Error ioctl\n"); - return -EFAULT; - } - - ret = _mtc_config(dev, &mtc_cfg); - } - break; + { + struct lsi_mtc_cfg_t mtc_cfg; + if (copy_from_user + ((void *)&mtc_cfg, (void *)arg, sizeof(mtc_cfg))) { + printk(KERN_DEBUG "MTC Error ioctl\n"); + return -EFAULT; + } + + ret = _mtc_config(dev, &mtc_cfg); + } + break; case MTC_SINGLESTEP_ENABLE: - { - struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t cfg0 = {0}; - int single_step; - if (copy_from_user((void *) &single_step, (void *) arg, sizeof(int))) { - printk(KERN_DEBUG"MTC Error ioctl\n"); - return -EFAULT; - } - - if ((single_step != 0) && (single_step != 1)) - return -EINVAL; - - cfg0 = - *((struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t *) &(dev->regs->config0)); - cfg0.single_step_en = single_step; - dev->regs->config0 = *((u32 *) &cfg0); - #ifdef DEBUG - printk(KERN_DEBUG"MTC_SINGLESTEP_ENABLE: dev->regs->config0=0x%x\n", - dev->regs->config0); - #endif - } - - break; - - case MTC_LOOPMODE_ENABLE: - { - struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t cfg0 = {0}; - int loop_mode; - if (copy_from_user((void *) &loop_mode, (void *) arg, sizeof(int))) { - printk(KERN_DEBUG"MTC Error ioctl\n"); - return -EFAULT; - } - - if ((loop_mode != 0) && (loop_mode != 1)) - return -EINVAL; + { + struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t cfg0 = { 0 }; + int single_step; + if (copy_from_user + ((void *)&single_step, (void *)arg, sizeof(int))) { + printk(KERN_DEBUG "MTC Error ioctl\n"); + return -EFAULT; + } + + if ((single_step != 0) && (single_step != 1)) + return -EINVAL; + + cfg0 = + *((struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t *) + &(dev->regs->config0)); + cfg0.single_step_en = single_step; + dev->regs->config0 = *((u32 *) &cfg0); +#ifdef DEBUG + printk(KERN_DEBUG + "MTC_SINGLESTEP_ENABLE: dev->regs->config0=0x%x\n", + dev->regs->config0); +#endif + } - cfg0 = - *((struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t *) &(dev->regs->config0)); - cfg0.loop_en = loop_mode; - dev->regs->config0 = *((u32 *) &cfg0); - #ifdef DEBUG - printk(KERN_DEBUG"MTC_LOOPMODE_ENABLE dev->regs->config0=0x%x\n", - dev->regs->config0); - #endif - } + break; + + case MTC_LOOPMODE_ENABLE: + { + struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t cfg0 = { 0 }; + int loop_mode; + if (copy_from_user + ((void *)&loop_mode, (void *)arg, sizeof(int))) { + printk(KERN_DEBUG "MTC Error ioctl\n"); + return -EFAULT; + } + + if ((loop_mode != 0) && (loop_mode != 1)) + return -EINVAL; + + cfg0 = + *((struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t *) + &(dev->regs->config0)); + cfg0.loop_en = loop_mode; + dev->regs->config0 = *((u32 *) &cfg0); +#ifdef DEBUG + printk(KERN_DEBUG + "MTC_LOOPMODE_ENABLE dev->regs->config0=0x%x\n", + dev->regs->config0); +#endif + } - break; + break; case MTC_RESET: - { - struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t exec1 = {0}; - exec1.sw_reset = 1; - dev->regs->execute = *((u32 *) &exec1); - #ifdef DEBUG - printk(KERN_DEBUG"dev->regs->execute=0x%x \n", dev->regs->execute); - #endif - } + { + struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t exec1 = { 0 }; + exec1.sw_reset = 1; + dev->regs->execute = *((u32 *) &exec1); +#ifdef DEBUG + printk(KERN_DEBUG "dev->regs->execute=0x%x\n", + dev->regs->execute); +#endif + } - break; + break; case MTC_TCKCLK_GATE: - { - struct lsi_mtc_tckclk_gate_t tckGate; - struct ncp_axis_mtc_MTC_CONFIG1_REG_ADDR_r_t cfg1 = {0}; - - if (copy_from_user((void *) &tckGate, (void *) arg, sizeof(tckGate))) { - printk(KERN_DEBUG"MTC Error ioctl\n"); - return -EFAULT; - } - - if (((tckGate.gate_tck_test_logic_reset != 0) - && (tckGate.gate_tck_test_logic_reset != 1)) - || ((tckGate.gate_tck != 0) && (tckGate.gate_tck != 1))) - return -EINVAL; - - cfg1 = - *((struct ncp_axis_mtc_MTC_CONFIG1_REG_ADDR_r_t *) &(dev->regs->config1)); - cfg1.sw_gate_tck_test_logic_reset = tckGate.gate_tck_test_logic_reset; - cfg1.sw_gate_tck = tckGate.gate_tck; - dev->regs->config1 = *((u32 *) &cfg1); - #ifdef DEBUG - printk(KERN_DEBUG"dev->regs->config1=0x%x \n", dev->regs->config1); - #endif - } - - break; - - case MTC_STARTSTOP_EXEC: - { - struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t cfg0 = {0}; - int start_stop; - if (copy_from_user((void *) &start_stop, (void *) arg, sizeof(int))) { - printk(KERN_DEBUG"MTC Error ioctl\n"); - return -EFAULT; - } - - if ((start_stop != 0) && (start_stop != 1)) - return -EINVAL; + { + struct lsi_mtc_tckclk_gate_t tckGate; + struct ncp_axis_mtc_MTC_CONFIG1_REG_ADDR_r_t cfg1 = { 0 }; + + if (copy_from_user + ((void *)&tckGate, (void *)arg, sizeof(tckGate))) { + printk(KERN_DEBUG "MTC Error ioctl\n"); + return -EFAULT; + } + + if (((tckGate.gate_tck_test_logic_reset != 0) + && (tckGate.gate_tck_test_logic_reset != 1)) + || ((tckGate.gate_tck != 0) + && (tckGate.gate_tck != 1))) + return -EINVAL; + + cfg1 = + *((struct ncp_axis_mtc_MTC_CONFIG1_REG_ADDR_r_t *) + &(dev->regs->config1)); + cfg1.sw_gate_tck_test_logic_reset = + tckGate.gate_tck_test_logic_reset; + cfg1.sw_gate_tck = tckGate.gate_tck; + dev->regs->config1 = *((u32 *) &cfg1); +#ifdef DEBUG + printk(KERN_DEBUG "dev->regs->config1=0x%x\n", + dev->regs->config1); +#endif + } - cfg0 = - *((struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t *) &(dev->regs->config0)); - cfg0.start_stopn = start_stop; - dev->regs->config0 = *((u32 *) &cfg0); - #ifdef DEBUG - printk(KERN_DEBUG"dev->regs->config0=0x%x \n", dev->regs->config0); - #endif - } + break; + + case MTC_STARTSTOP_EXEC: + { + struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t cfg0 = { 0 }; + int start_stop; + if (copy_from_user + ((void *)&start_stop, (void *)arg, sizeof(int))) { + printk(KERN_DEBUG "MTC Error ioctl\n"); + return -EFAULT; + } + + if ((start_stop != 0) && (start_stop != 1)) + return -EINVAL; + + cfg0 = + *((struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t *) + &(dev->regs->config0)); + cfg0.start_stopn = start_stop; + dev->regs->config0 = *((u32 *) &cfg0); +#ifdef DEBUG + printk(KERN_DEBUG "dev->regs->config0=0x%x\n", + dev->regs->config0); +#endif + } - break; + break; case MTC_SINGLESTEP_EXEC: - { - struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t exec1 = {0}; - exec1.single_step = 1; - dev->regs->execute = *((u32 *) &exec1); - pr_debug("dev->regs->execute=0x%x \n", dev->regs->execute); + { + struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t exec1 = { 0 }; + exec1.single_step = 1; + dev->regs->execute = *((u32 *) &exec1); + pr_debug("dev->regs->execute=0x%x\n", + dev->regs->execute); - } - break; + } + break; case MTC_CONTINUE_EXEC: - { - struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t exec1 = {0}; - exec1.cont_after_pause = 1; - dev->regs->execute = *((u32 *) &exec1); - pr_debug("dev->regs->execute=0x%x \n", dev->regs->execute); + { + struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t exec1 = { 0 }; + exec1.cont_after_pause = 1; + dev->regs->execute = *((u32 *) &exec1); + pr_debug("dev->regs->execute=0x%x\n", + dev->regs->execute); - } - break; + } + break; case MTC_READ_STATS: - { - struct lsi_mtc_stats_regs_t stats; + { + struct lsi_mtc_stats_regs_t stats; - stats.statsReg1 = dev->regs->status1; - stats.statsReg2 = dev->regs->status2; + stats.statsReg1 = dev->regs->status1; + stats.statsReg2 = dev->regs->status2; - if (copy_to_user((void *)arg, &stats, sizeof(stats))) - return -EFAULT; + if (copy_to_user((void *)arg, &stats, sizeof(stats))) + return -EFAULT; - } - break; + } + break; case MTC_READ_DEBUG: - { - struct lsi_mtc_debug_regs_t debug; + { + struct lsi_mtc_debug_regs_t debug; - debug.debugReg0 = dev->regs->debug0; - debug.debugReg1 = dev->regs->debug1; - debug.debugReg2 = dev->regs->debug2; - debug.debugReg3 = dev->regs->debug3; - debug.debugReg4 = dev->regs->debug4; - debug.debugReg5 = dev->regs->debug5; + debug.debugReg0 = dev->regs->debug0; + debug.debugReg1 = dev->regs->debug1; + debug.debugReg2 = dev->regs->debug2; + debug.debugReg3 = dev->regs->debug3; + debug.debugReg4 = dev->regs->debug4; + debug.debugReg5 = dev->regs->debug5; - if (copy_to_user((void *)arg, &debug, sizeof(debug))) - return -EFAULT; - - } + if (copy_to_user((void *)arg, &debug, sizeof(debug))) + return -EFAULT; - break; + } + break; default: - printk(KERN_DEBUG"Invalid ioctl cmd=%d MTC_DEBUG_OP=%d\n", - cmd, MTC_DEBUG_OP); - ret = -EINVAL; + printk(KERN_DEBUG "Invalid ioctl cmd=%d MTC_DEBUG_OP=%d\n", + cmd, MTC_DEBUG_OP); + ret = -EINVAL; } @@ -2813,18 +2818,16 @@ mtc_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) } static const struct file_operations mtc_char_ops = { - .owner = THIS_MODULE, - .open = mtc_dev_open, - .release = mtc_dev_release, - .llseek = generic_file_llseek, - .read = mtc_dev_read, - .write = mtc_dev_write, + .owner = THIS_MODULE, + .open = mtc_dev_open, + .release = mtc_dev_release, + .llseek = generic_file_llseek, + .read = mtc_dev_read, + .write = mtc_dev_write, .unlocked_ioctl = mtc_dev_ioctl }; - -static irqreturn_t -mtc_isr(int irq_no, void *arg) +static irqreturn_t mtc_isr(int irq_no, void *arg) { struct mtc_device *priv = arg; u32 status = readl(&priv->regs->int_status); @@ -2845,15 +2848,14 @@ mtc_isr(int irq_no, void *arg) * * Initialize device. */ -static int __devinit -mtc_probe(struct platform_device *pdev) +static int __devinit mtc_probe(struct platform_device *pdev) { -static struct mtc_device *dev; + static struct mtc_device *dev; void __iomem *regs; int rc; - printk(KERN_DEBUG"!!!!MTC: mtc_probe()\n"); - /* Allocate space for device private data */ + printk(KERN_DEBUG "!!!!MTC: mtc_probe()\n"); + /* Allocate space for device private data */ dev = kzalloc(sizeof *dev, GFP_KERNEL); if (!dev) { rc = -ENOMEM; @@ -2870,14 +2872,14 @@ static struct mtc_device *dev; goto err; } #ifdef __MTC_SIMULATION - dev->regs = &_mtc_regs; - dev->prgmem = _mtc_prgmem; - dev->tdomem = _mtc_tdomem; + dev->regs = &_mtc_regs; + dev->prgmem = _mtc_prgmem; + dev->tdomem = _mtc_tdomem; #else - dev->regs = regs; - dev->prgmem = regs + MTC_PRGMEM_OFFSET/4; - dev->tdomem = regs + MTC_TDOMEM_OFFSET/4; + dev->regs = regs; + dev->prgmem = (u32 *) regs + MTC_PRGMEM_OFFSET / 4; + dev->tdomem = (u32 *) regs + MTC_TDOMEM_OFFSET / 4; #endif /* Attach to IRQ */ dev->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); @@ -2893,8 +2895,8 @@ static struct mtc_device *dev; */ dev->char_device.minor = MISC_DYNAMIC_MINOR; - dev->char_device.name = "mtc"; - dev->char_device.fops = &mtc_char_ops; + dev->char_device.name = "mtc"; + dev->char_device.fops = &mtc_char_ops; rc = misc_register(&dev->char_device); if (rc) @@ -2903,7 +2905,7 @@ static struct mtc_device *dev; return 0; -err: + err: if (dev) kref_put(&dev->ref, mtc_destroy); dev_err(&pdev->dev, "Failed to probe device (%d)\n", rc); @@ -2913,8 +2915,7 @@ err: /** * mtc_remove */ -static int __devexit -mtc_remove(struct platform_device *pdev) +static int __devexit mtc_remove(struct platform_device *pdev) { struct mtc_device *dev = dev_get_drvdata(&pdev->dev); kref_put(&dev->ref, mtc_destroy); @@ -2926,8 +2927,7 @@ mtc_remove(struct platform_device *pdev) * * Called when refcount reaches zero to unregister device and free resources. */ -static void -mtc_destroy(struct kref *ref) +static void mtc_destroy(struct kref *ref) { struct mtc_device *dev = container_of(ref, struct mtc_device, ref); @@ -2940,16 +2940,13 @@ mtc_destroy(struct kref *ref) kfree(dev); } - #ifdef CONFIG_PM -static int -mtc_suspend(struct platform_device *pdev, pm_message_t state) +static int mtc_suspend(struct platform_device *pdev, pm_message_t state) { return -ENOSYS; } -static int -mtc_resume(struct platform_device *pdev) +static int mtc_resume(struct platform_device *pdev) { return -ENOSYS; } @@ -2959,20 +2956,20 @@ mtc_resume(struct platform_device *pdev) #endif static const struct of_device_id mtc_of_ids[] = { - { .compatible = "lsi,mtc" }, + {.compatible = "lsi,mtc"}, {} }; static struct platform_driver mtc_driver = { .driver = { - .name = "mtc", - .owner = THIS_MODULE, - .of_match_table = mtc_of_ids, - }, - .probe = mtc_probe, - .remove = mtc_remove, - .suspend = mtc_suspend, - .resume = mtc_resume + .name = "mtc", + .owner = THIS_MODULE, + .of_match_table = mtc_of_ids, + }, + .probe = mtc_probe, + .remove = mtc_remove, + .suspend = mtc_suspend, + .resume = mtc_resume }; module_platform_driver(mtc_driver); @@ -2982,10 +2979,9 @@ MODULE_DESCRIPTION("Master Test Controller driver"); MODULE_LICENSE("GPL"); /* MTC operating mode. */ -#define LSI_MTC_BOARDTEST_MODE 0 /* MTC Board Test Mode. */ -#define LSI_MTC_EXTTEST_MODE 1 /* MTC External Test Mode DBC3 excluded. */ -#define LSI_MTC_SYSTTEST_MODE 2/* MTC System Test Mode DBC3 excluded. */ - +#define LSI_MTC_BOARDTEST_MODE 0 /* MTC Board Test Mode. */ +#define LSI_MTC_EXTTEST_MODE 1 /* MTC External Test Mode DBC3 excluded. */ +#define LSI_MTC_SYSTTEST_MODE 2 /* MTC System Test Mode DBC3 excluded. */ /* Test data output recording mode. */ /* Do not save TDO data during shiftir and shiftdr. */ @@ -3004,39 +3000,40 @@ MODULE_LICENSE("GPL"); and inactive in all other states. */ #define LSI_MTC_TDOBUF_TRISTATE_CAPABLE 1 - - /* config MTC hardware */ -static long _mtc_config(struct mtc_device *dev, - struct lsi_mtc_cfg_t *pMTCCfg) +static long _mtc_config(struct mtc_device *dev, struct lsi_mtc_cfg_t *pMTCCfg) { - struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t cfg0 = {0}; - struct ncp_axis_mtc_MTC_CONFIG1_REG_ADDR_r_t cfg1 = {0}; - struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t exec1 = {0}; + struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t cfg0 = { 0 }; + struct ncp_axis_mtc_MTC_CONFIG1_REG_ADDR_r_t cfg1 = { 0 }; + struct ncp_axis_mtc_MTC_EXECUTE1_REG_ADDR_r_t exec1 = { 0 }; if ((!pMTCCfg) || (!dev)) return -EINVAL; /* 1. stop testgen state machine */ cfg0 = - *((struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t *) &(dev->regs->config0)); + *((struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t *) + &(dev->regs->config0)); cfg0.start_stopn = 0; - dev->regs->config0 = *((u32 *) &cfg0); + dev->regs->config0 = *((u32 *) &cfg0); - /* 2. reset testgen */ + /* 2. reset testgen, and init mem */ exec1.sw_reset = 1; dev->regs->execute = *((u32 *) &exec1); + dev->regs->mem_init = 0x202; /* 3. config MTC */ cfg0 = - *((struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t *) &(dev->regs->config0)); + *((struct ncp_axis_mtc_MTC_CONFIG0_REG_ADDR_r_t *) + &(dev->regs->config0)); cfg1 = - *((struct ncp_axis_mtc_MTC_CONFIG1_REG_ADDR_r_t *) &(dev->regs->config1)); + *((struct ncp_axis_mtc_MTC_CONFIG1_REG_ADDR_r_t *) + &(dev->regs->config1)); /*set MTC mode */ - if (pMTCCfg->opMode == LSI_MTC_BOARDTEST_MODE) { + if (pMTCCfg->opMode == LSI_MTC_BOARDTEST_MODE) { /* board testing mode */ cfg0.cfg_config_ctl = 0; } else if (pMTCCfg->opMode == LSI_MTC_EXTTEST_MODE) { @@ -3059,27 +3056,29 @@ static long _mtc_config(struct mtc_device *dev, cfg1.record_tdo_in_shift_ir_state = 0; cfg1.record_tdo_in_shift_dr_state = 0; } else if (pMTCCfg->recMode == LSI_MTC_TDO_NOREC_SHIFTIR) { - cfg1.record_tdo_in_shift_ir_state = 1; - cfg1.record_tdo_in_shift_dr_state = 0; + cfg1.record_tdo_in_shift_ir_state = 0; + cfg1.record_tdo_in_shift_dr_state = 1; } else if (pMTCCfg->recMode == LSI_MTC_TDO_NOREC_SHIFTDR) { - cfg1.record_tdo_in_shift_ir_state = 1; - cfg1.record_tdo_in_shift_dr_state = 0; + cfg1.record_tdo_in_shift_ir_state = 0; + cfg1.record_tdo_in_shift_dr_state = 1; } else { /* recMode == ACELL_MTCI_TDO_REC_ALL */ cfg1.record_tdo_in_shift_ir_state = 1; cfg1.record_tdo_in_shift_dr_state = 1; } - dev->regs->config0 = *((u32 *) &cfg0); - dev->regs->config1 = *((u32 *) &cfg1); + dev->regs->config0 = *((u32 *) &cfg0); + dev->regs->config1 = *((u32 *) &cfg1); #ifdef DEBUG - printk(KERN_DEBUG"buffmode=%d,rate=%d dev->regs->config0 =0x%x \n", - pMTCCfg->buffMode, pMTCCfg->clkSpeed, dev->regs->config0); + printk(KERN_DEBUG "buffmode=%d,rate=%d dev->regs->config0 =0x%x\n", + pMTCCfg->buffMode, pMTCCfg->clkSpeed, dev->regs->config0); - printk(KERN_DEBUG"dev->regs->config1 =0x%x, dev->regs-> execute=0x%x \n", - dev->regs->config1, dev->regs->execute); + printk(KERN_DEBUG + "dev->regs->config1 =0x%x, dev->regs-> execute=0x%x\n", + dev->regs->config1, dev->regs->execute); #endif + /* test */ return 0; } -- 1.7.9.5 -- _______________________________________________ linux-yocto mailing list linux-yocto@yoctoproject.org https://lists.yoctoproject.org/listinfo/linux-yocto