On 7/1/15 9:57 AM, Saul Wold wrote: > As part of the larger breaking up of x86 put the Intel Vendor Enablers > in their own file > > Signed-off-by: Saul Wold <s...@linux.intel.com> > --- > meta/cfg/kernel-cache/cfg/intel.cfg | 19 +++++++++++++++++++ > meta/cfg/kernel-cache/cfg/intel.scc | 1 + > 2 files changed, 20 insertions(+) > create mode 100644 meta/cfg/kernel-cache/cfg/intel.cfg > create mode 100644 meta/cfg/kernel-cache/cfg/intel.scc > > diff --git a/meta/cfg/kernel-cache/cfg/intel.cfg > b/meta/cfg/kernel-cache/cfg/intel.cfg > new file mode 100644 > index 0000000..108022e > --- /dev/null > +++ b/meta/cfg/kernel-cache/cfg/intel.cfg > @@ -0,0 +1,19 @@ > +# Config settings specific to intel processors > +CONFIG_MICROCODE=y > +CONFIG_MICROCODE_INTEL=y > +CONFIG_MICROCODE_EARLY=y > +CONFIG_MICROCODE_INTEL_EARLY=y > + > + > +CONFIG_PROCESSOR_SELECT=y > +CONFIG_CPU_SUP_INTEL=y > + > +CONFIG_X86_EXTENDED_PLATFORM=y > +CONFIG_X86_PLATFORM_DEVICES=y > +CONFIG_X86_INTEL_MID=y > +CONFIG_X86_INTEL_QUARK=y > +CONFIG_X86_INTEL_LPSS=y
I was going to push back on LPSS, like with PCI and hotplug, but it's a single option here, contained properly to intel.cfg, and unlikely to be not wanted on any recent, current, or near future SoC as far as I can tell.... so this is actually fine with me. -- Darren Hart Intel Open Source Technology Center -- _______________________________________________ linux-yocto mailing list linux-yocto@yoctoproject.org https://lists.yoctoproject.org/listinfo/linux-yocto
