From: Alexandre Belloni <alexandre.bell...@free-electrons.com>

CUPD is not flushed before enabling the channel so it will update
CDTY/CPRD just after one period. So we always set CUPD, even when the
channel is not enabled.

Signed-off-by: Alexandre Belloni <alexandre.bell...@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.fe...@atmel.com>
Signed-off-by: Thierry Reding <thierry.red...@gmail.com>
(cherry picked from commit 4c027f7ba8520df088d34ae045205a6f8e2a1d76)
Signed-off-by: Tan Jui Nee <jui.nee....@intel.com>
---
 drivers/pwm/pwm-atmel.c | 35 ++++++++++++++++++-----------------
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index d3c22de..89f9ca4 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -155,24 +155,25 @@ static void atmel_pwm_config_v1(struct pwm_chip *chip, 
struct pwm_device *pwm,
        struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
        unsigned int val;
 
-       if (test_bit(PWMF_ENABLED, &pwm->flags)) {
-               /*
-                * If the PWM channel is enabled, using the update register,
-                * it needs to set bit 10 of CMR to 0
-                */
-               atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
 
-               val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
-               val &= ~PWM_CMR_UPD_CDTY;
-               atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
-       } else {
-               /*
-                * If the PWM channel is disabled, write value to duty and
-                * period registers directly.
-                */
-               atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
-               atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
-       }
+       atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
+
+       val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
+       val &= ~PWM_CMR_UPD_CDTY;
+       atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
+
+       /*
+        * If the PWM channel is enabled, only update CDTY by using the update
+        * register, it needs to set bit 10 of CMR to 0
+        */
+       if (test_bit(PWMF_ENABLED, &pwm->flags))
+               return;
+       /*
+        * If the PWM channel is disabled, write value to duty and period
+        * registers directly.
+        */
+       atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
+       atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
 }
 
 static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
-- 
1.9.1

-- 
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