From: John Jacques <john.jacq...@intel.com>
Simplify the clock definitions in the device tree. Only
the peripheral clock frequency is needed and it is fixed.
The boot loader will determine the frequency and update
the device tree before booting Linux.
Signed-off-by: John Jacques <john.jacq...@intel.com>
---
arch/arm64/boot/dts/intel/axc67xx.dtsi | 85 ++--
arch/arm64/boot/dts/intel/axm56xx.dtsi | 44 +-
drivers/clk/Makefile | 1 -
drivers/clk/clk-axm5516.c | 614 ---------------------------
include/dt-bindings/clock/lsi,axm5516-clks.h | 36 --
5 files changed, 54 insertions(+), 726 deletions(-)
delete mode 100644 drivers/clk/clk-axm5516.c
delete mode 100644 include/dt-bindings/clock/lsi,axm5516-clks.h
diff --git a/arch/arm64/boot/dts/intel/axc67xx.dtsi
b/arch/arm64/boot/dts/intel/axc67xx.dtsi
index 46fd578..719ca97 100644
--- a/arch/arm64/boot/dts/intel/axc67xx.dtsi
+++ b/arch/arm64/boot/dts/intel/axc67xx.dtsi
@@ -10,7 +10,6 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/lsi,axm5516-clks.h>
/ {
#address-cells = <2>;
@@ -53,21 +52,14 @@
};
clocks {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #address-cells = <1>;
+ #size-cells = <0>;
- clk_ref {
+ clk_per: clk_per {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- clks: dummy-clock {
- compatible = "fixed-clock";
- #clock-cells = <1>;
- clock-frequency = <100000000>;
+ clock-frequency = <0>; /* Set by the Boot Loader */
+ clock-output-names = "clk_per";
};
};
@@ -202,7 +194,7 @@
#size-cells = <0>;
reg = <0x80 0x80600000 0 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -213,7 +205,7 @@
#size-cells = <0>;
reg = <0x80 0x80610000 0 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -224,7 +216,7 @@
#size-cells = <0>;
reg = <0x80 0x80620000 0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -235,7 +227,7 @@
#size-cells = <0>;
reg = <0x80 0x80630000 0 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -246,7 +238,7 @@
#size-cells = <0>;
reg = <0x80 0x80640000 0 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -257,7 +249,7 @@
#size-cells = <0>;
reg = <0x80 0x80650000 0 0x1000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -268,7 +260,7 @@
#size-cells = <0>;
reg = <0x80 0x80660000 0 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -279,7 +271,7 @@
#size-cells = <0>;
reg = <0x80 0x80670000 0 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -290,7 +282,7 @@
#size-cells = <0>;
reg = <0x80 0x80680000 0 0x1000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -301,7 +293,7 @@
#size-cells = <0>;
reg = <0x80 0x80690000 0 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -312,7 +304,7 @@
#size-cells = <0>;
reg = <0x80 0x806a0000 0 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -323,7 +315,7 @@
#size-cells = <0>;
reg = <0x80 0x806b0000 0 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -334,7 +326,7 @@
#size-cells = <0>;
reg = <0x80 0x806c0000 0 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -417,7 +409,7 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x80 0x80000000 0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -426,7 +418,7 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x80 0x80010000 0 0x10000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -435,7 +427,7 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x80 0x80020000 0 0x10000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -451,7 +443,7 @@
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
};
@@ -461,7 +453,7 @@
gpio-controller;
reg = <0x80 0x80700000 0 0x10000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -472,7 +464,7 @@
gpio-controller;
reg = <0x80 0x80710000 0 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -483,7 +475,7 @@
gpio-controller;
reg = <0x80 0x80720000 0 0x10000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -494,7 +486,7 @@
gpio-controller;
reg = <0x80 0x80730000 0 0x10000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -505,7 +497,7 @@
gpio-controller;
reg = <0x80 0x80740000 0 0x10000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -516,7 +508,7 @@
gpio-controller;
reg = <0x80 0x80750000 0 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -527,7 +519,7 @@
gpio-controller;
reg = <0x80 0x80760000 0 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -538,7 +530,7 @@
gpio-controller;
reg = <0x80 0x80770000 0 0x10000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -548,7 +540,7 @@
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x80 0x80780000 0 0x10000>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -558,7 +550,7 @@
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x80 0x80790000 0 0x10000>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -568,7 +560,7 @@
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x80 0x807a0000 0 0x10000>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -578,7 +570,7 @@
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x80 0x807b0000 0 0x10000>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -591,8 +583,7 @@
reg = <0x80 0x80100000 0 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <5>;
- clocks = <&clks AXXIA_CLK_PER>, <&clks
AXXIA_CLK_PER>;
- clock-names = "spi", "apb_pclk";
+ clocks = <&clk_per 0>;
status = "disabled";
};
@@ -604,8 +595,7 @@
reg = <0x80 0x80110000 0 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <5>;
- clocks = <&clks AXXIA_CLK_PER>, <&clks
AXXIA_CLK_PER>;
- clock-names = "spi", "apb_pclk";
+ clocks = <&clk_per 0>;
status = "disabled";
};
@@ -617,8 +607,7 @@
reg = <0x80 0x80120000 0 0x1000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <5>;
- clocks = <&clks AXXIA_CLK_PER>, <&clks
AXXIA_CLK_PER>;
- clock-names = "spi", "apb_pclk";
+ clocks = <&clk_per 0>;
status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/intel/axm56xx.dtsi
b/arch/arm64/boot/dts/intel/axm56xx.dtsi
index 5ac6c36..b1b6f73 100644
--- a/arch/arm64/boot/dts/intel/axm56xx.dtsi
+++ b/arch/arm64/boot/dts/intel/axm56xx.dtsi
@@ -10,7 +10,6 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/lsi,axm5516-clks.h>
/ {
#address-cells = <2>;
@@ -42,21 +41,14 @@
};
clocks {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #address-cells = <1>;
+ #size-cells = <0>;
- clk_ref {
+ clk_per: clk_per {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- clks: dummy-clock {
- compatible = "fixed-clock";
- #clock-cells = <1>;
- clock-frequency = <100000000>;
+ clock-frequency = <0>; /* Set by the Boot Loader */
+ clock-output-names = "clk_per";
};
};
@@ -182,7 +174,7 @@
#size-cells = <0>;
reg = <0x80 0x80080000 0 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -193,7 +185,7 @@
#size-cells = <0>;
reg = <0x80 0x80090000 0 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -204,7 +196,7 @@
#size-cells = <0>;
reg = <0x80 0x800a0000 0 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -215,7 +207,7 @@
#size-cells = <0>;
reg = <0x80 0x800b0000 0 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "i2c";
status = "disabled";
};
@@ -345,7 +337,7 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x80 0x80000000 0 0x10000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -354,7 +346,7 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x80 0x80010000 0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -363,7 +355,7 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x80 0x80020000 0 0x10000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -372,7 +364,7 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x80 0x80030000 0 0x10000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -388,7 +380,7 @@
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
};
@@ -405,7 +397,7 @@
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -416,7 +408,7 @@
gpio-controller;
reg = <0x80 0x80190000 0 0x10000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks AXXIA_CLK_PER>;
+ clocks = <&clk_per 0>;
clock-names = "apb_pclk";
status = "disabled";
};
@@ -429,9 +421,7 @@
reg = <0x80 0x80100000 0 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <5>;
- clocks = <&clks AXXIA_CLK_PER>,
- <&clks AXXIA_CLK_PER>;
- clock-names = "spi", "apb_pclk";
+ clocks = <&clk_per 0>;
status = "disabled";
};
};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3d00c25..70a00b8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -18,7 +18,6 @@ endif
# please keep this section sorted lexicographically by file/directory path name
obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
-obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
diff --git a/drivers/clk/clk-axm5516.c b/drivers/clk/clk-axm5516.c
deleted file mode 100644
index c7c91a5..0000000
--- a/drivers/clk/clk-axm5516.c
+++ /dev/null
@@ -1,614 +0,0 @@
-/*
- * drivers/clk/clk-axm5516.c
- *
- * Provides clock implementations for three different types of clock devices on
- * the Axxia device: PLL clock, a clock divider and a clock mux.
- *
- * Copyright (C) 2014 LSI Corporation
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/clk-provider.h>
-#include <linux/regmap.h>
-#include <dt-bindings/clock/lsi,axm5516-clks.h>
-
-
-/**
- * struct axxia_clk - Common struct to all Axxia clocks.
- * @hw: clk_hw for the common clk framework
- * @regmap: Regmap for the clock control registers
- */
-struct axxia_clk {
- struct clk_hw hw;
- struct regmap *regmap;
-};
-#define to_axxia_clk(_hw) container_of(_hw, struct axxia_clk, hw)
-
-/**
- * struct axxia_pllclk - Axxia PLL generated clock.
- * @aclk: Common struct
- * @reg: Offset into regmap for PLL control register
- */
-struct axxia_pllclk {
- struct axxia_clk aclk;
- u32 reg;
-};
-#define to_axxia_pllclk(_aclk) container_of(_aclk, struct axxia_pllclk, aclk)
-
-/**
- * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
- * parent clock rate.
- */
-static unsigned long
-axxia_pllclk_recalc(struct clk_hw *hw, unsigned long parent_rate)
-{
- struct axxia_clk *aclk = to_axxia_clk(hw);
- struct axxia_pllclk *pll = to_axxia_pllclk(aclk);
- unsigned long rate, fbdiv, refdiv, postdiv;
- u32 control;
-
- regmap_read(aclk->regmap, pll->reg, &control);
- postdiv = ((control >> 0) & 0xf) + 1;
- fbdiv = ((control >> 4) & 0xfff) + 3;
- refdiv = ((control >> 16) & 0x1f) + 1;
- rate = (parent_rate / (refdiv * postdiv)) * fbdiv;
-
- return rate;
-}
-
-static const struct clk_ops axxia_pllclk_ops = {
- .recalc_rate = axxia_pllclk_recalc,
-};
-
-/**
- * struct axxia_divclk - Axxia clock divider
- * @aclk: Common struct
- * @reg: Offset into regmap for PLL control register
- * @shift: Bit position for divider value
- * @width: Number of bits in divider value
- */
-struct axxia_divclk {
- struct axxia_clk aclk;
- u32 reg;
- u32 shift;
- u32 width;
-};
-#define to_axxia_divclk(_aclk) container_of(_aclk, struct axxia_divclk, aclk)
-
-/**
- * axxia_divclk_recalc_rate - Calculate clock divider output rage
- */
-static unsigned long
-axxia_divclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-{
- struct axxia_clk *aclk = to_axxia_clk(hw);
- struct axxia_divclk *divclk = to_axxia_divclk(aclk);
- u32 ctrl, div;
-
- regmap_read(aclk->regmap, divclk->reg, &ctrl);
- div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1));
-
- return parent_rate / div;
-}
-
-static const struct clk_ops axxia_divclk_ops = {
- .recalc_rate = axxia_divclk_recalc_rate,
-};
-
-/**
- * struct axxia_clkmux - Axxia clock mux
- * @aclk: Common struct
- * @reg: Offset into regmap for PLL control register
- * @shift: Bit position for selection value
- * @width: Number of bits in selection value
- */
-struct axxia_clkmux {
- struct axxia_clk aclk;
- u32 reg;
- u32 shift;
- u32 width;
-};
-#define to_axxia_clkmux(_aclk) container_of(_aclk, struct axxia_clkmux, aclk)
-
-/**
- * axxia_clkmux_get_parent - Return the index of selected parent clock
- */
-static u8 axxia_clkmux_get_parent(struct clk_hw *hw)
-{
- struct axxia_clk *aclk = to_axxia_clk(hw);
- struct axxia_clkmux *mux = to_axxia_clkmux(aclk);
- u32 ctrl, parent;
-
- regmap_read(aclk->regmap, mux->reg, &ctrl);
- parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1);
-
- return (u8) parent;
-}
-
-static const struct clk_ops axxia_clkmux_ops = {
- .get_parent = axxia_clkmux_get_parent,
-};
-
-
-/*
- * PLLs
- */
-
-static struct axxia_pllclk clk_fab_pll = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_fab_pll",
- .parent_names = (const char *[]){
- "clk_ref0"
- },
- .num_parents = 1,
- .ops = &axxia_pllclk_ops,
- },
- .reg = 0x01800,
-};
-
-static struct axxia_pllclk clk_cpu_pll = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_cpu_pll",
- .parent_names = (const char *[]){
- "clk_ref0"
- },
- .num_parents = 1,
- .ops = &axxia_pllclk_ops,
- },
- .reg = 0x02000,
-};
-
-static struct axxia_pllclk clk_sys_pll = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_sys_pll",
- .parent_names = (const char *[]){
- "clk_ref0"
- },
- .num_parents = 1,
- .ops = &axxia_pllclk_ops,
- },
- .reg = 0x02800,
-};
-
-static struct axxia_pllclk clk_sm0_pll = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_sm0_pll",
- .parent_names = (const char *[]){
- "clk_ref2"
- },
- .num_parents = 1,
- .ops = &axxia_pllclk_ops,
- },
- .reg = 0x03000,
-};
-
-static struct axxia_pllclk clk_sm1_pll = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_sm1_pll",
- .parent_names = (const char *[]){
- "clk_ref1"
- },
- .num_parents = 1,
- .ops = &axxia_pllclk_ops,
- },
- .reg = 0x03800,
-};
-
-/*
- * Clock dividers
- */
-
-static struct axxia_divclk clk_cpu0_div = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_cpu0_div",
- .parent_names = (const char *[]){
- "clk_cpu_pll"
- },
- .num_parents = 1,
- .ops = &axxia_divclk_ops,
- },
- .reg = 0x10008,
- .shift = 0,
- .width = 4,
-};
-
-static struct axxia_divclk clk_cpu1_div = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_cpu1_div",
- .parent_names = (const char *[]){
- "clk_cpu_pll"
- },
- .num_parents = 1,
- .ops = &axxia_divclk_ops,
- },
- .reg = 0x10008,
- .shift = 4,
- .width = 4,
-};
-
-static struct axxia_divclk clk_cpu2_div = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_cpu2_div",
- .parent_names = (const char *[]){
- "clk_cpu_pll"
- },
- .num_parents = 1,
- .ops = &axxia_divclk_ops,
- },
- .reg = 0x10008,
- .shift = 8,
- .width = 4,
-};
-
-static struct axxia_divclk clk_cpu3_div = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_cpu3_div",
- .parent_names = (const char *[]){
- "clk_cpu_pll"
- },
- .num_parents = 1,
- .ops = &axxia_divclk_ops,
- },
- .reg = 0x10008,
- .shift = 12,
- .width = 4,
-};
-
-static struct axxia_divclk clk_nrcp_div = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_nrcp_div",
- .parent_names = (const char *[]){
- "clk_sys_pll"
- },
- .num_parents = 1,
- .ops = &axxia_divclk_ops,
- },
- .reg = 0x1000c,
- .shift = 0,
- .width = 4,
-};
-
-static struct axxia_divclk clk_sys_div = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_sys_div",
- .parent_names = (const char *[]){
- "clk_sys_pll"
- },
- .num_parents = 1,
- .ops = &axxia_divclk_ops,
- },
- .reg = 0x1000c,
- .shift = 4,
- .width = 4,
-};
-
-static struct axxia_divclk clk_fab_div = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_fab_div",
- .parent_names = (const char *[]){
- "clk_fab_pll"
- },
- .num_parents = 1,
- .ops = &axxia_divclk_ops,
- },
- .reg = 0x1000c,
- .shift = 8,
- .width = 4,
-};
-
-static struct axxia_divclk clk_per_div = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_per_div",
- .parent_names = (const char *[]){
- "clk_sm1_pll"
- },
- .num_parents = 1,
- .flags = CLK_IS_BASIC,
- .ops = &axxia_divclk_ops,
- },
- .reg = 0x1000c,
- .shift = 12,
- .width = 4,
-};
-
-static struct axxia_divclk clk_mmc_div = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_mmc_div",
- .parent_names = (const char *[]){
- "clk_sm1_pll"
- },
- .num_parents = 1,
- .flags = CLK_IS_BASIC,
- .ops = &axxia_divclk_ops,
- },
- .reg = 0x1000c,
- .shift = 16,
- .width = 4,
-};
-
-/*
- * Clock MUXes
- */
-
-static struct axxia_clkmux clk_cpu0_mux = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_cpu0",
- .parent_names = (const char *[]){
- "clk_ref0",
- "clk_cpu_pll",
- "clk_cpu0_div",
- "clk_cpu0_div"
- },
- .num_parents = 4,
- .ops = &axxia_clkmux_ops,
- },
- .reg = 0x10000,
- .shift = 0,
- .width = 2,
-};
-
-static struct axxia_clkmux clk_cpu1_mux = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_cpu1",
- .parent_names = (const char *[]){
- "clk_ref0",
- "clk_cpu_pll",
- "clk_cpu1_div",
- "clk_cpu1_div"
- },
- .num_parents = 4,
- .ops = &axxia_clkmux_ops,
- },
- .reg = 0x10000,
- .shift = 2,
- .width = 2,
-};
-
-static struct axxia_clkmux clk_cpu2_mux = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_cpu2",
- .parent_names = (const char *[]){
- "clk_ref0",
- "clk_cpu_pll",
- "clk_cpu2_div",
- "clk_cpu2_div"
- },
- .num_parents = 4,
- .ops = &axxia_clkmux_ops,
- },
- .reg = 0x10000,
- .shift = 4,
- .width = 2,
-};
-
-static struct axxia_clkmux clk_cpu3_mux = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_cpu3",
- .parent_names = (const char *[]){
- "clk_ref0",
- "clk_cpu_pll",
- "clk_cpu3_div",
- "clk_cpu3_div"
- },
- .num_parents = 4,
- .ops = &axxia_clkmux_ops,
- },
- .reg = 0x10000,
- .shift = 6,
- .width = 2,
-};
-
-static struct axxia_clkmux clk_nrcp_mux = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_nrcp",
- .parent_names = (const char *[]){
- "clk_ref0",
- "clk_sys_pll",
- "clk_nrcp_div",
- "clk_nrcp_div"
- },
- .num_parents = 4,
- .ops = &axxia_clkmux_ops,
- },
- .reg = 0x10004,
- .shift = 0,
- .width = 2,
-};
-
-static struct axxia_clkmux clk_sys_mux = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_sys",
- .parent_names = (const char *[]){
- "clk_ref0",
- "clk_sys_pll",
- "clk_sys_div",
- "clk_sys_div"
- },
- .num_parents = 4,
- .ops = &axxia_clkmux_ops,
- },
- .reg = 0x10004,
- .shift = 2,
- .width = 2,
-};
-
-static struct axxia_clkmux clk_fab_mux = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_fab",
- .parent_names = (const char *[]){
- "clk_ref0",
- "clk_fab_pll",
- "clk_fab_div",
- "clk_fab_div"
- },
- .num_parents = 4,
- .ops = &axxia_clkmux_ops,
- },
- .reg = 0x10004,
- .shift = 4,
- .width = 2,
-};
-
-static struct axxia_clkmux clk_per_mux = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_per",
- .parent_names = (const char *[]){
- "clk_ref1",
- "clk_per_div"
- },
- .num_parents = 2,
- .ops = &axxia_clkmux_ops,
- },
- .reg = 0x10004,
- .shift = 6,
- .width = 1,
-};
-
-static struct axxia_clkmux clk_mmc_mux = {
- .aclk.hw.init = &(struct clk_init_data){
- .name = "clk_mmc",
- .parent_names = (const char *[]){
- "clk_ref1",
- "clk_mmc_div"
- },
- .num_parents = 2,
- .ops = &axxia_clkmux_ops,
- },
- .reg = 0x10004,
- .shift = 9,
- .width = 1,
-};
-
-/* Table of all supported clocks indexed by the clock identifiers from the
- * device tree binding
- */
-static struct axxia_clk *axmclk_clocks[] = {
- [AXXIA_CLK_FAB_PLL] = &clk_fab_pll.aclk,
- [AXXIA_CLK_CPU_PLL] = &clk_cpu_pll.aclk,
- [AXXIA_CLK_SYS_PLL] = &clk_sys_pll.aclk,
- [AXXIA_CLK_SM0_PLL] = &clk_sm0_pll.aclk,
- [AXXIA_CLK_SM1_PLL] = &clk_sm1_pll.aclk,
- [AXXIA_CLK_FAB_DIV] = &clk_fab_div.aclk,
- [AXXIA_CLK_SYS_DIV] = &clk_sys_div.aclk,
- [AXXIA_CLK_NRCP_DIV] = &clk_nrcp_div.aclk,
- [AXXIA_CLK_CPU0_DIV] = &clk_cpu0_div.aclk,
- [AXXIA_CLK_CPU1_DIV] = &clk_cpu1_div.aclk,
- [AXXIA_CLK_CPU2_DIV] = &clk_cpu2_div.aclk,
- [AXXIA_CLK_CPU3_DIV] = &clk_cpu3_div.aclk,
- [AXXIA_CLK_PER_DIV] = &clk_per_div.aclk,
- [AXXIA_CLK_MMC_DIV] = &clk_mmc_div.aclk,
- [AXXIA_CLK_FAB] = &clk_fab_mux.aclk,
- [AXXIA_CLK_SYS] = &clk_sys_mux.aclk,
- [AXXIA_CLK_NRCP] = &clk_nrcp_mux.aclk,
- [AXXIA_CLK_CPU0] = &clk_cpu0_mux.aclk,
- [AXXIA_CLK_CPU1] = &clk_cpu1_mux.aclk,
- [AXXIA_CLK_CPU2] = &clk_cpu2_mux.aclk,
- [AXXIA_CLK_CPU3] = &clk_cpu3_mux.aclk,
- [AXXIA_CLK_PER] = &clk_per_mux.aclk,
- [AXXIA_CLK_MMC] = &clk_mmc_mux.aclk,
-};
-
-static const struct regmap_config axmclk_regmap_config = {
- .reg_bits = 32,
- .reg_stride = 4,
- .val_bits = 32,
- .max_register = 0x1fffc,
- .fast_io = true,
-};
-
-static const struct of_device_id axmclk_match_table[] = {
- { .compatible = "lsi,axm5516-clks" },
- { }
-};
-MODULE_DEVICE_TABLE(of, axmclk_match_table);
-
-struct axmclk_priv {
- struct clk_onecell_data onecell;
- struct clk *clks[];
-};
-
-static int axmclk_probe(struct platform_device *pdev)
-{
- void __iomem *base;
- struct resource *res;
- int i, ret;
- struct device *dev = &pdev->dev;
- struct clk *clk;
- struct regmap *regmap;
- size_t num_clks;
- struct axmclk_priv *priv;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(dev, res);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- regmap = devm_regmap_init_mmio(dev, base, &axmclk_regmap_config);
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
-
- num_clks = ARRAY_SIZE(axmclk_clocks);
- pr_info("axmclk: supporting %zu clocks\n", num_clks);
- priv = devm_kzalloc(dev, sizeof(*priv) + sizeof(*priv->clks) * num_clks,
- GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
-
- priv->onecell.clks = priv->clks;
- priv->onecell.clk_num = num_clks;
-
- /* Update each entry with the allocated regmap and register the clock
- * with the common clock framework
- */
- for (i = 0; i < num_clks; i++) {
- axmclk_clocks[i]->regmap = regmap;
- clk = devm_clk_register(dev, &axmclk_clocks[i]->hw);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
- priv->clks[i] = clk;
- }
-
- ret = of_clk_add_provider(dev->of_node,
- of_clk_src_onecell_get, &priv->onecell);
-
- return ret;
-}
-
-static int axmclk_remove(struct platform_device *pdev)
-{
- of_clk_del_provider(pdev->dev.of_node);
- return 0;
-}
-
-static struct platform_driver axmclk_driver = {
- .probe = axmclk_probe,
- .remove = axmclk_remove,
- .driver = {
- .name = "clk-axm5516",
- .of_match_table = axmclk_match_table,
- },
-};
-
-static int __init axmclk_init(void)
-{
- return platform_driver_register(&axmclk_driver);
-}
-core_initcall(axmclk_init);
-
-static void __exit axmclk_exit(void)
-{
- platform_driver_unregister(&axmclk_driver);
-}
-module_exit(axmclk_exit);
-
-MODULE_DESCRIPTION("AXM5516 clock driver");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:clk-axm5516");
diff --git a/include/dt-bindings/clock/lsi,axm5516-clks.h
b/include/dt-bindings/clock/lsi,axm5516-clks.h
deleted file mode 100644
index beb41ac..0000000
--- a/include/dt-bindings/clock/lsi,axm5516-clks.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2014 LSI Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- */
-
-#ifndef _DT_BINDINGS_CLK_AXM5516_H
-#define _DT_BINDINGS_CLK_AXM5516_H
-
-#define AXXIA_CLK_FAB_PLL 0
-#define AXXIA_CLK_CPU_PLL 1
-#define AXXIA_CLK_SYS_PLL 2
-#define AXXIA_CLK_SM0_PLL 3
-#define AXXIA_CLK_SM1_PLL 4
-#define AXXIA_CLK_FAB_DIV 5
-#define AXXIA_CLK_SYS_DIV 6
-#define AXXIA_CLK_NRCP_DIV 7
-#define AXXIA_CLK_CPU0_DIV 8
-#define AXXIA_CLK_CPU1_DIV 9
-#define AXXIA_CLK_CPU2_DIV 10
-#define AXXIA_CLK_CPU3_DIV 11
-#define AXXIA_CLK_PER_DIV 12
-#define AXXIA_CLK_MMC_DIV 13
-#define AXXIA_CLK_FAB 14
-#define AXXIA_CLK_SYS 15
-#define AXXIA_CLK_NRCP 16
-#define AXXIA_CLK_CPU0 17
-#define AXXIA_CLK_CPU1 18
-#define AXXIA_CLK_CPU2 19
-#define AXXIA_CLK_CPU3 20
-#define AXXIA_CLK_PER 21
-#define AXXIA_CLK_MMC 22
-
-#endif
--
2.7.4
--
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