From: Gary McGee <gary.mc...@intel.com>
Only allow officially supported configurations.
Signed-off-by: Gary McGee <gary.mc...@intel.com>
---
drivers/misc/axxia-pei.c | 474 ++++++++++--------------------------------
drivers/pci/host/pcie-axxia.c | 7 -
2 files changed, 108 insertions(+), 373 deletions(-)
diff --git a/drivers/misc/axxia-pei.c b/drivers/misc/axxia-pei.c
index a221bf5..a620216 100644
--- a/drivers/misc/axxia-pei.c
+++ b/drivers/misc/axxia-pei.c
@@ -855,7 +855,7 @@ static int check_ack(u32 phy, u32 lane, enum Dir dir)
return regVal;
}
-static int check_srio_ack(enum SrioMode mode)
+int check_srio_ack(enum SrioMode mode)
{
unsigned int phy;
unsigned int lane;
@@ -1174,7 +1174,7 @@ update_settings(void)
*/
static int
-pei_setup(unsigned int control)
+pei_setup_56xx(unsigned int control)
{
unsigned int pci_srio_sata_mode;
unsigned int rc_mode;
@@ -1192,13 +1192,9 @@ pei_setup(unsigned int control)
unsigned int pei1_mode;
unsigned int pei2_mode;
u32 reg_val = 0;
- int phy, lane;
+ int phy;
pci_srio_sata_mode = (control & 0x03c00000) >> 22;
- /*
- pr_debug("YYY: pei_setup control=0x%08x pci_srio_sata_mode=%d\n",
- control, pci_srio_sata_mode);
- */
sata0_mode = (control & 0x20) >> 5;
sata1_mode = (control & 0x40) >> 6;
@@ -1238,26 +1234,11 @@ pei_setup(unsigned int control)
mdelay(100); /* TODO: Why is this needed? */
switch (pci_srio_sata_mode) {
- case 0:
- set_sw_port_config0(pc0_PEI0x8);
- set_sw_port_config1(pc1_PEI0x8);
- set_pei0_rc_mode(rc_mode);
- set_pipe_port_sel(pp_0);
- set_pipe_nphy(four_phy);
-
- if (pei0_mode)
- for (phy = 0; phy < 4; phy++)
- release_reset(phy);
- /* Enable PEI0 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0x0, ®_val);
- reg_val |= (pei0_mode << 0);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0x0, reg_val);
- break;
case 1:
/*
- PEI0x4, PEI1x4
- */
+ * PEI0x4 + PEI1x4
+ */
set_sw_port_config0(pc0_PEI0x4);
set_sw_port_config1(pc1_PEI1x4);
set_pei0_rc_mode(rc_mode);
@@ -1278,67 +1259,11 @@ pei_setup(unsigned int control)
(pei1_mode << 1);
ncr_write32(NCP_REGION_ID(0x115, 0), 0x0, reg_val);
break;
- case 2:
- /* PEI0x4_PEI1x2_SATA0x1_SATA1x1 */
- /* Enable PEI0/PEI1, PEI0 RC mode */
- set_sw_port_config0(pc0_PEI0x4);
- set_sw_port_config1(pc1_PEI1x2_SATA0x1_SATA1x1);
- set_pei0_rc_mode(rc_mode);
- set_pipe_port_sel(pp_0_1);
- if (pei0_mode)
- for (phy = 0; phy < 2; phy++)
- release_reset(phy);
- if (pei1_mode)
- release_reset(2);
-
- /* Enable PEI0/PEI1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (pei0_mode << 0) | (pei1_mode << 1);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
-
- if (sata0_mode)
- setup_sata_mode(SATA0, sata0_speed);
- if (sata1_mode)
- setup_sata_mode(SATA1, sata1_speed);
- if (sata0_mode || sata1_mode) {
- release_reset(3);
- for (lane = 0; lane < 2; lane++) {
- if (!check_ack(3, lane, TX)) {
- pr_err("TX ACK not set for PHY3
LANE%d\n",
- lane);
- return 1;
- }
- if (!check_ack(3, lane, RX)) {
- pr_err("RX ACK not set for PHY3
LANE%d\n",
- lane);
- return 1;
- }
- }
-
- /* Set TX clock ready */
- set_tx_clk_ready();
- }
-
- /* Enable SATA0/SATA1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (sata0_mode << 29) | (sata1_mode << 30);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
-
- if (sata0_mode || sata1_mode) {
- if (!check_rx_valid(3, 0)) {
- pr_err("RX clock/data recovery not asserted for
PHY3 LANE0\n");
- return 1;
- }
- if (!check_rx_valid(3, 1)) {
- pr_err("RX clock/data recovery not asserted for
PHY3 LANE1\n");
- return 1;
- }
- }
- break;
- case 3:
- /* PEI0x2_PEI2x2 */
- /* PEI1x2_SATA0_SATA1 */
+ case 2:
+ /*
+ * PEI0x2 + PEI2x2 + PEI1x2 + UNUSED (SATA0_SATA1)
+ */
set_sw_port_config0(pc0_PEI0x2_PEI2x2);
set_sw_port_config1(pc1_PEI1x2_SATA0x1_SATA1x1);
set_pei0_rc_mode(rc_mode);
@@ -1357,6 +1282,7 @@ pei_setup(unsigned int control)
(pei2_mode << 2);
ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
+#if 0
if (sata0_mode)
setup_sata_mode(SATA0, sata0_speed);
if (sata1_mode)
@@ -1394,137 +1320,13 @@ pei_setup(unsigned int control)
return 1;
}
}
+#endif
break;
- case 4:
- /* PEI0x2_SRIO0x2_PEI1x4 */
- /* Enable PEI0/PEI1/SRIO0, PEI0 RC mode */
- set_sw_port_config0(pc0_PEI0x2_SRIO0x2);
- set_sw_port_config1(pc1_PEI1x4);
- set_pei0_rc_mode(rc_mode);
- set_pipe_port_sel(pp_0_1);
- if (pei0_mode)
- release_reset(0);
- if (pei1_mode)
- for (phy = 2; phy < 4; phy++)
- release_reset(phy);
- /* Enable PEI0/PEI1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (pei0_mode << 0) | (pei1_mode << 1);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
-
- set_srio_mode(SRIO0, srio0_ctrl);
- set_srio_speed(SRIO0, srio0_speed);
- pr_debug("Set up sRIO0 -- %d\n", srio0_speed);
- if (srio0_mode && release_srio_reset(SRIO0, srio0_speed))
- srio0_mode = 0;
- pr_debug("Enabling sRIO .");
- if (srio0_mode && check_srio_ack(SRIO0))
- srio0_mode = 0;
- /* Power up TX/RX lanes */
- if (srio0_mode && powerup_srio_lanes(SRIO0, P1))
- srio0_mode = 0;
- /* Set TX clock ready */
- if (srio0_mode)
- set_tx_clk_ready();
- if (srio0_mode && powerup_srio_lanes(SRIO0, P0))
- srio0_mode = 0;
- if (srio0_mode)
- enable_srio_lanes(SRIO0);
- /* Enable SRIO0 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (srio0_mode << 3);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
- pr_debug("Done\n");
- break;
- case 5:
- /* PEI0x2_SRIO0x2_PEI1x2_SATA0x1_SATA1x1 */
- /* Enable PEI0/PEI1/SRIO0, PEI0 RC mode */
- set_sw_port_config0(pc0_PEI0x2_SRIO0x2);
- set_sw_port_config1(pc1_PEI1x2_SATA0x1_SATA1x1);
- set_pei0_rc_mode(rc_mode);
- set_pipe_port_sel(pp_0_1);
- set_pipe_nphy(three_phy);
-
- if (pei0_mode)
- release_reset(0);
- if (pei1_mode)
- release_reset(2);
-
- /* Enable PEI0/PEI1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (pei0_mode << 0) | (pei1_mode << 1);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
-
- set_srio_mode(SRIO0, srio0_ctrl);
- set_srio_speed(SRIO0, srio0_speed);
-
- if (sata0_mode)
- setup_sata_mode(SATA0, sata0_speed);
- if (sata1_mode)
- setup_sata_mode(SATA1, sata1_speed);
- if (srio0_mode)
- setup_srio_mode(SRIO0, srio0_speed);
- pr_debug("Set up sRIO0 -- %d\n", srio0_speed);
- if (srio0_mode && release_srio_reset(SRIO0, srio0_speed))
- srio0_mode = 0;
- if (sata0_mode || sata1_mode)
- release_reset(3);
- if (sata0_mode || sata1_mode) {
- for (lane = 0; lane < 2; lane++) {
- if (!check_ack(3, lane, TX)) {
- pr_err("TX ACK not set for PHY3
LANE%d\n",
- lane);
- return 1;
- }
- if (!check_ack(3, lane, RX)) {
- pr_err("RX ACK not set for PHY3
LANE%d\n",
- lane);
- return 1;
- }
- }
- }
- pr_debug("Enabling sRIO/SATA .");
- if (srio0_mode && check_srio_ack(SRIO0))
- srio0_mode = 0;
- if (srio0_mode && powerup_srio_lanes(SRIO0, P1))
- srio0_mode = 0;
-
- /* Set TX clock ready */
- if (srio0_mode || sata0_mode || sata1_mode)
- set_tx_clk_ready();
-
- if (srio0_mode && powerup_srio_lanes(SRIO0, P0))
- srio0_mode = 0;
- if (srio0_mode)
- enable_srio_lanes(SRIO0);
-
- /* Enable SATA0/SATA1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (sata0_mode << 29) | (sata1_mode << 30);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
-
- if (sata0_mode || sata1_mode) {
- if (!check_rx_valid(3, 0)) {
- pr_err("RX clock/data recovery not asserted for
PHY3 LANE0\n");
- return 1;
- }
- if (!check_rx_valid(3, 1)) {
- pr_err("RX clock/data recovery not asserted for
PHY3 LANE1\n");
- return 1;
- }
- }
-
- /* Enable SRIO0 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (srio0_mode << 3);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
- pr_debug("Done\n");
- break;
- case 6:
- /* PEI0x2_SRIO0x2_PEI1x2_PEI2x2 */
- /* Enable PEI0/PEI1/PEI2/SRIO0, PEI0 RC mode */
+ case 3:
+ /* PEI0x2 + SRIO0x2 + UNUSED (PEI1x2) + PEI2x2 */
+ /* Enable PEI0/PEI2/SRIO0, PEI0 RC mode */
set_pei0_rc_mode(rc_mode);
set_sw_port_config0(pc0_PEI0x2_SRIO0x2);
set_sw_port_config1(pc1_PEI1x2_PEI2x2);
@@ -1533,15 +1335,12 @@ pei_setup(unsigned int control)
if (pei0_mode)
release_reset(0);
- if (pei1_mode)
- release_reset(2);
if (pei2_mode)
release_reset(3);
/* Enable PEI0/PEI1/PEI2 */
ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (pei0_mode << 0) | (pei1_mode << 1) |
- (pei2_mode << 2);
+ reg_val |= (pei0_mode << 0) | (pei2_mode << 2);
ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
set_srio_mode(SRIO0, srio0_ctrl);
@@ -1572,166 +1371,21 @@ pei_setup(unsigned int control)
ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
pr_debug("Done\n");
break;
- case 7:
- /* SRIO1x2_SRIO0x2_PEI1x4 */
- /* Enable PEI1/SRIO0/SRIO1 */
- set_sw_port_config0(pc0_SRIO1x2_SRIO0x2);
- set_sw_port_config1(pc1_PEI1x4);
- set_pipe_port_sel(pp_0_1);
- set_pipe_nphy(four_phy);
- if (pei1_mode)
- for (phy = 2; phy < 4; phy++)
- release_reset(phy);
- /* Enable PEI1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (pei1_mode << 1);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
- set_srio_mode(SRIO0, srio0_ctrl);
- set_srio_mode(SRIO1, srio1_ctrl);
- set_srio_speed(SRIO0, srio0_speed);
- set_srio_speed(SRIO1, srio1_speed);
- pr_debug("Set up sRIO0 -- %d\n", srio0_speed);
- if (srio0_mode) {
- setup_srio_mode(SRIO0, srio0_speed);
- if (release_srio_reset(SRIO0, srio0_speed))
- srio0_mode = 0;
- }
- pr_debug("Set up sRIO1 -- %d\n", srio1_speed);
- if (srio1_mode) {
- setup_srio_mode(SRIO1, srio1_speed);
- if (release_srio_reset(SRIO1, srio1_speed))
- srio1_mode = 0;
- }
- pr_debug("Enabling sRIO .");
- /* Power up TX/RX lanes */
- if (srio0_mode) {
- pr_debug("0 .");
- if (powerup_srio_lanes(SRIO0, P1))
- srio0_mode = 0;
- }
- if (srio1_mode) {
- pr_debug("1 .");
- if (powerup_srio_lanes(SRIO1, P1))
- srio1_mode = 0;
- }
- pr_debug(".");
- /* Set TX clock ready */
- if (srio0_mode || srio1_mode)
- set_tx_clk_ready();
-
- /* Power up TX/RX lanes */
- if (srio0_mode && powerup_srio_lanes(SRIO0, P0))
- srio0_mode = 0;
- if (srio1_mode && powerup_srio_lanes(SRIO1, P0))
- srio1_mode = 0;
- pr_debug(".");
- if (srio0_mode)
- enable_srio_lanes(SRIO0);
- if (srio1_mode)
- enable_srio_lanes(SRIO1);
- pr_debug(".");
- /* Enable SRIO0/SRIO1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (srio0_mode << 3) | (srio1_mode << 10);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
- pr_debug("Done\n");
- break;
- case 8:
- /* SRIO1x2_SRIO0x2_PEI1x2_SATA0x1_SATA1x1 */
- /* Enable PEI1 */
- set_sw_port_config0(pc0_SRIO1x2_SRIO0x2);
- set_sw_port_config1(pc1_PEI1x2_SATA0x1_SATA1x1);
- set_pipe_port_sel(pp_0_1);
- set_pipe_nphy(two_phy);
-
- if (pei1_mode)
- release_reset(2);
-
- /* Enable PEI1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (pei1_mode << 1);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
-
- set_srio_mode(SRIO0, srio0_ctrl);
- set_srio_mode(SRIO1, srio1_ctrl);
- set_srio_speed(SRIO0, srio0_speed);
- set_srio_speed(SRIO1, srio1_speed);
- if (sata0_mode)
- setup_sata_mode(SATA0, sata0_speed);
- if (sata1_mode)
- setup_sata_mode(SATA1, sata1_speed);
- pr_debug("Set up sRIO0 -- %d\n", srio0_speed);
- if (srio0_mode) {
- setup_srio_mode(SRIO0, srio0_speed);
- if (release_srio_reset(SRIO0, srio0_speed))
- srio0_mode = 0;
- }
- pr_debug("Set up sRIO1 -- %d\n", srio1_speed);
- if (srio1_mode) {
- setup_srio_mode(SRIO1, srio1_speed);
- if (release_srio_reset(SRIO1, srio1_speed))
- srio1_mode = 0;
- }
- if (sata0_mode || sata1_mode)
- release_reset(3);
-
- pr_debug("Enabling sRIO/SATA .");
- /* Power up TX/RX lanes */
- if (srio0_mode && powerup_srio_lanes(SRIO0, P1))
- srio0_mode = 0;
- if (srio1_mode && powerup_srio_lanes(SRIO1, P1))
- srio1_mode = 0;
-
- pr_debug(".");
- /* Set TX clock ready */
- if (srio0_mode || srio1_mode || sata0_mode || sata1_mode)
- set_tx_clk_ready();
-
- /* Power up TX/RX lanes */
- if (srio0_mode && powerup_srio_lanes(SRIO0, P0))
- srio0_mode = 0;
- if (srio1_mode && powerup_srio_lanes(SRIO1, P0))
- srio1_mode = 0;
- pr_debug(".");
-
- if (srio0_mode)
- enable_srio_lanes(SRIO0);
- if (srio1_mode)
- enable_srio_lanes(SRIO1);
- pr_debug(".");
-
- /* Enable SATA0/SATA1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (sata0_mode << 29) | (sata1_mode << 30);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
-
- if (sata0_mode && !check_rx_valid(3, 0))
- pr_err("RX clock/data recovery not asserted for PHY3
LANE0\n");
- if (sata1_mode && !check_rx_valid(3, 1))
- pr_err("RX clock/data recovery not asserted for PHY3
LANE1\n");
- /* Enable SRIO0/SRIO1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (srio0_mode << 3) | (srio1_mode << 10);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
- pr_debug("Done\n");
- break;
- case 9:
- /* SRIO1x2_SRIO0x2_PEI1x2_PEI2x2 */
+ case 4:
+ /* SRIO1x2 + SRIO0x2 + UNUSED(PEI1x2) + PEI2x2 */
/* Enable PEI2/PEI1 */
set_sw_port_config0(pc0_SRIO1x2_SRIO0x2);
set_sw_port_config1(pc1_PEI1x2_PEI2x2);
set_pipe_port_sel(pp_0_1_2_3);
- if (pei1_mode)
- release_reset(2);
if (pei2_mode)
release_reset(3);
/* Enable PEI1/PEI2 */
ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (pei1_mode << 1) | (pei2_mode << 2);
+ reg_val |= (pei2_mode << 2);
ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
set_srio_mode(SRIO0, srio0_ctrl);
@@ -1780,6 +1434,89 @@ pei_setup(unsigned int control)
ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
pr_debug("Done\n");
break;
+
+ default:
+ pr_err("axxia_pei: invalid PCI/SRIO config\n");
+ pr_err("pei_setup control=0x%08x pci_srio_sata_mode=%d\n",
+ control, pci_srio_sata_mode);
+
+ return -1;
+ }
+
+
+ update_settings();
+
+ return 0;
+}
+
+static int
+pei_setup_67xx(unsigned int control)
+{
+ unsigned int pci_mode;
+ unsigned int rc_mode;
+ unsigned int pei0_mode;
+ u32 reg_val = 0;
+
+ pci_mode = (control & 0x00c00000) >> 22;
+
+ pei0_mode = (control & 0x1);
+
+ rc_mode = (control & 0x80) >> 7;
+
+ if (pei0_mode)
+ disable_ltssm(PEI0);
+
+ /* enable serdes reset */
+ enable_reset(0);
+
+ /* Disable pei0 interfaces */
+ ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
+ reg_val &= ~(0x1);
+ ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
+ mdelay(100); /* TODO: Why is this needed? */
+
+ switch (pci_mode) {
+
+ case 1:
+ /*
+ * PEI0x2
+ */
+ set_pei0_rc_mode(rc_mode);
+ set_pipe_port_sel(pp_0);
+ set_pipe_nphy(one_phy);
+
+ if (pei0_mode)
+ release_reset(0);
+
+ /* Enable PEI0 */
+ ncr_read32(NCP_REGION_ID(0x115, 0), 0x0, ®_val);
+ reg_val |= (pei0_mode << 0);
+ ncr_write32(NCP_REGION_ID(0x115, 0), 0x0, reg_val);
+ break;
+
+ case 2:
+ /*
+ * PEI0x1
+ */
+ set_pei0_rc_mode(rc_mode);
+ set_pipe_port_sel(pp_0);
+ set_pipe_nphy(one_phy);
+
+ if (pei0_mode)
+ release_reset(0);
+
+ /* Enable PEI0 */
+ ncr_read32(NCP_REGION_ID(0x115, 0), 0x0, ®_val);
+ reg_val |= (pei0_mode << 0);
+ ncr_write32(NCP_REGION_ID(0x115, 0), 0x0, reg_val);
+ break;
+
+ default:
+ pr_err("axxia_pei: invalid PCI/SRIO config\n");
+ pr_err("pei_setup control=0x%08x pci_mode=%d\n",
+ control, pci_mode);
+
+ return -1;
}
@@ -1787,7 +1524,6 @@ pei_setup(unsigned int control)
return 0;
}
-EXPORT_SYMBOL(pei_setup);
/*
------------------------------------------------------------------------------
@@ -1835,6 +1571,7 @@ get_v2_coefficients(struct device_node *pei_control)
int axxia_pei_setup(unsigned int control, unsigned int force)
{
int ret = 0;
+ int rv = -1;
mutex_lock(&axxia_pei_mux);
@@ -1855,7 +1592,12 @@ int axxia_pei_setup(unsigned int control, unsigned int
force)
assumption.
*/
if (0 == axxia_pei.initialized) {
- if (0 != pei_setup(control)) {
+ if (is_5600)
+ rv = pei_setup_56xx(control);
+ else if (is_6700)
+ rv = pei_setup_67xx(control);
+
+ if (0 != rv) {
pr_err("pcie-axxia: PEI setup failed!\n");
ret = -EINVAL;
diff --git a/drivers/pci/host/pcie-axxia.c b/drivers/pci/host/pcie-axxia.c
index 7bc54e0..05430e3 100644
--- a/drivers/pci/host/pcie-axxia.c
+++ b/drivers/pci/host/pcie-axxia.c
@@ -976,13 +976,6 @@ static int axxia_pcie_probe(struct platform_device *pdev)
pp->root_bus_nr = 0;
pei_control = of_find_node_by_name(NULL, "pei_control");
- /* LTSSM disable */
- axxia_cc_gpreg_readl(pp, PEI_GENERAL_CORE_CTL_REG, &val);
- msleep(100);
- val &= ~(0x1);
- axxia_cc_gpreg_writel(pp, val, PEI_GENERAL_CORE_CTL_REG);
- msleep(100);
-
if (pei_control) {
control = of_get_property(pei_control, "control", NULL);
--
2.7.4
--
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