From: Marek Majtyka <marekx.majt...@intel.com> Added cache L1/L2/L3, SMEM and CMEM drivers. Changes: - added dtsi/dts definition for XLF board - separated configuration between X9 and XLF - fix issue with nca ring access - added tracepoints for L3 cache - other small code adjustments.
Signed-off-by: Marek Majtyka <marekx.majt...@intel.com> --- .../devicetree/bindings/arm/axxia/edac_l1.txt | 15 +++ .../devicetree/bindings/arm/axxia/edac_l2.txt | 5 +- .../devicetree/bindings/arm/axxia/edac_l3.txt | 11 ++- arch/arm64/boot/dts/intel/axc6732-waco.dts | 32 ++++++ arch/arm64/boot/dts/intel/axc67xx.dtsi | 68 +++++++++++++ drivers/edac/Kconfig | 34 +++++++ drivers/edac/Makefile | 4 + drivers/edac/axxia_edac-cmc_56xx.c | 8 +- drivers/edac/axxia_edac-l2_cpu_56xx.c | 31 ++++++ drivers/edac/axxia_edac-l3_56xx.c | 78 ++++++++++++--- drivers/edac/axxia_edac-mc_56xx.c | 8 +- drivers/misc/lsi-ncr.c | 4 +- include/trace/events/edacl3.h | 109 +++++++++++++++++++++ 13 files changed, 385 insertions(+), 22 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/axxia/edac_l1.txt create mode 100644 include/trace/events/edacl3.h diff --git a/Documentation/devicetree/bindings/arm/axxia/edac_l1.txt b/Documentation/devicetree/bindings/arm/axxia/edac_l1.txt new file mode 100644 index 0000000..5e0a8dc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/axxia/edac_l1.txt @@ -0,0 +1,15 @@ +Axxia Error Detection & Correction [EDAC] +The EDAC accesses ARM v7/v8 L2MERRSR_EL1 register data. + +Required properties: +- compatible : should contain "intel,cortex-a53-cpu" for AXM67xx + : should contain "intel,cortex-a57-cpu" for AXM56xx + : should contain "lsi,cortex-a15-cpu" for AXM55xx +- syscon : should referernce syscon node for both 55xx/56xx/67xx + +Example: + edac_l2: edac_l2 { + compatible = "intel,cortex-a57-cpu"; + syscon = <&syscon>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/arm/axxia/edac_l2.txt b/Documentation/devicetree/bindings/arm/axxia/edac_l2.txt index d90629c..b99e77a 100644 --- a/Documentation/devicetree/bindings/arm/axxia/edac_l2.txt +++ b/Documentation/devicetree/bindings/arm/axxia/edac_l2.txt @@ -2,9 +2,10 @@ Axxia Error Detection & Correction [EDAC] The EDAC accesses ARM v7/v8 L2MERRSR_EL1 register data. Required properties: -- compatible : should contain "intel,cortex-a57-l2-cache" for AXM56xx +- compatible : should contain "intel,cortex-a53-l2-cache" for AXM67xx + : should contain "intel,cortex-a57-l2-cache" for AXM56xx : should contain "lsi,cortex-a15-l2-cache" for AXM55xx -- syscon : should referernce syscon node for both 55xx/56xx +- syscon : should referernce syscon node for both 55xx/56xx/67xx Example: edac_l2: edac_l2 { diff --git a/Documentation/devicetree/bindings/arm/axxia/edac_l3.txt b/Documentation/devicetree/bindings/arm/axxia/edac_l3.txt index e37b5b8..5b80f21 100644 --- a/Documentation/devicetree/bindings/arm/axxia/edac_l3.txt +++ b/Documentation/devicetree/bindings/arm/axxia/edac_l3.txt @@ -2,7 +2,8 @@ Axxia Error Detection & Correction [EDAC] The EDAC accesses a range of registers in the dickens l3 controller Required properties: -- compatible : should contain "intel,ccn504-l3-cache" +- compatible : should contain "intel,ccn504-l3-cache" + : should contain "intel,ccn512-l3-cache" - reg : should contain address of ccn first node; its range shall contain all ccn nodes registers ( 0x1000000 ). - interrupts : if given driver uses interrupts, if not poll mechanism applies @@ -15,3 +16,11 @@ Example: syscon = <&syscon>; status = "disabled"; }; + + edac_l3: edac_l3 { + compatible = "intel,ccn512-l3-cache"; + reg = <0x40 0x00000000 0 0x1000000>; + interrupts = <0 432 4>; + syscon = <&syscon>; + status = "disabled"; + }; diff --git a/arch/arm64/boot/dts/intel/axc6732-waco.dts b/arch/arm64/boot/dts/intel/axc6732-waco.dts index c600dbe..c76c984 100644 --- a/arch/arm64/boot/dts/intel/axc6732-waco.dts +++ b/arch/arm64/boot/dts/intel/axc6732-waco.dts @@ -250,6 +250,18 @@ status = "okay"; }; +&edac_cpu { + status = "okay"; +}; + +&edac_l2 { + status = "okay"; +}; + +&edac_l3 { + status = "okay"; +}; + &mtc { status = "okay"; }; @@ -257,3 +269,23 @@ &trng { status = "okay"; }; + +&sm0 { + status = "okay"; +}; + +&sm1 { + status = "okay"; +}; + +&sm2 { + status = "okay"; +}; + +&sm3 { + status = "okay"; +}; + +&cm0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/intel/axc67xx.dtsi b/arch/arm64/boot/dts/intel/axc67xx.dtsi index e0d100c..7bb4cd8 100644 --- a/arch/arm64/boot/dts/intel/axc67xx.dtsi +++ b/arch/arm64/boot/dts/intel/axc67xx.dtsi @@ -49,6 +49,14 @@ spi2 = &spi2; gpdma0 = &gpdma0; gpdma1 = &gpdma1; + edac_cpu = &edac_cpu; + edac_l2 = &edac_l2; + edac_l3 = &edac_l3; + sm0 = &sm0; + sm1 = &sm1; + sm2 = &sm2; + sm3 = &sm3; + cm0 = &cm0; }; clocks { @@ -104,6 +112,26 @@ reg = <0x80 0x02c00000 0 0x40000>; }; + edac_cpu: edac_cpu { + compatible = "intel,cortex-a53-cpu"; + syscon = <&syscon>; + status = "disabled"; + }; + + edac_l2: edac_l2 { + compatible = "intel,cortex-a53-l2-cache"; + syscon = <&syscon>; + status = "disabled"; + }; + + edac_l3: edac_l3 { + compatible = "intel,ccn512-l3-cache"; + reg = <0x40 0x00000000 0 0x1000000>; + interrupts = <0 432 4>; + syscon = <&syscon>; + status = "disabled"; + }; + reset: reset@2010031000 { compatible = "intel,axm56xx-reset"; syscon = <&syscon>; @@ -135,6 +163,46 @@ status = "disabled"; }; + sm0: sm0@00220000 { + compatible = "intel,smmon"; + reg = <0 0x00220000 0 0x1000>; + syscon = <&syscon>; + interrupts = <0 451 4>; + status = "disabled"; + }; + + sm1: sm1@000f0000 { + compatible = "intel,smmon"; + reg = <0 0x000f0000 0 0x1000>; + syscon = <&syscon>; + interrupts = <0 452 4>; + status = "disabled"; + }; + + sm2: sm2@00230000 { + compatible = "intel,smmon"; + reg = <0 0x00230000 0 0x1000>; + syscon = <&syscon>; + interrupts = <0 453 4>; + status = "disabled"; + }; + + sm3: sm3@00240000 { + compatible = "intel,smmon"; + reg = <0 0x00240000 0 0x1000>; + syscon = <&syscon>; + interrupts = <0 454 4>; + status = "disabled"; + }; + + cm0: cm0@00080009 { + compatible = "intel,cmmon"; + reg = <0 0x00080009 0 0x1000>; + syscon = <&syscon>; + interrupts = <0 386 4>; + status = "disabled"; + }; + usb0: usb@9000000000 { compatible = "intel,axxia-dwc3"; dma-coherent; diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 49713c3..2fd3734 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -404,6 +404,15 @@ config EDAC_AXXIA_SYSMEM_5500 the System Memory error detection. System Memory error detection is interrupt driven. +config EDAC_AXXIA_SYSMEM_6700 + depends on ARCH_AXXIA + bool "AXXIA EDAC SysMem Controller for 6700" + help + Support for System Memory Denali controller error + detection on the AXXIA AXM67xx devices. This enables + the System Memory error detection. System Memory error + detection is interrupt driven. + config EDAC_AXXIA_CMEM_5600 depends on ARCH_AXXIA bool "AXXIA EDAC CMem Controller for 5600" @@ -413,6 +422,15 @@ config EDAC_AXXIA_CMEM_5600 the Configuration Memory error detection. Configuration Memory error detection is interrupt driven. +config EDAC_AXXIA_CMEM_6700 + depends on ARCH_AXXIA + bool "AXXIA EDAC CMem Controller for 6700" + help + Support for Configuration Memory Denali controller error + detection on the AXXIA AXM67xx devices. This enables + the Configuration Memory error detection. Configuration Memory error + detection is interrupt driven. + config EDAC_AXXIA_L3_5500 tristate "AXXIA EDAC L3 Controller for 5500" help @@ -429,6 +447,14 @@ config EDAC_AXXIA_L3_5600 L3 cache error detection. L3 cache error detection uses polling mechanism. +config EDAC_AXXIA_L3_6700 + tristate "AXXIA EDAC L3 Controller for 6700" + help + Support for the eight L3 caches error detection + on the AXXIA AXM67xx devices. This enables the + L3 cache error detection. L3 cache error detection + can use polling mechanism or be interrupt driven. + config EDAC_AXXIA_L2_CPU_5500 tristate "AXXIA EDAC L2/CPU Controller for 5500" help @@ -445,6 +471,14 @@ config EDAC_AXXIA_L2_CPU_5600 cache and A57 CPU error detction. L2 cache and A57 CPU error detection uses polling mechanism. +config EDAC_AXXIA_L2_CPU_6700 + tristate "AXXIA EDAC L2/CPU Controller for 6700" + help + Support for L2 cache and A53 CPU error detection + on AXXIA AXM67xx devices. This enables the L2 + cache and A53 CPU error detction. L2 cache and A53 + CPU error detection uses polling mechanism. + config EDAC_ALTERA_MC tristate "Altera SDRAM Memory Controller EDAC" depends on EDAC_MM_EDAC && ARCH_SOCFPGA diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 7d215e0..b398821 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -18,11 +18,15 @@ endif obj-$(CONFIG_EDAC_AXXIA_SYSMEM_5500) += axxia_edac-mc.o obj-$(CONFIG_EDAC_AXXIA_SYSMEM_5600) += axxia_edac-mc_56xx.o +obj-$(CONFIG_EDAC_AXXIA_SYSMEM_6700) += axxia_edac-mc_56xx.o obj-$(CONFIG_EDAC_AXXIA_CMEM_5600) += axxia_edac-cmc_56xx.o +obj-$(CONFIG_EDAC_AXXIA_CMEM_6700) += axxia_edac-cmc_56xx.o obj-$(CONFIG_EDAC_AXXIA_L3_5500) += axxia_edac-l3.o obj-$(CONFIG_EDAC_AXXIA_L3_5600) += axxia_edac-l3_56xx.o +obj-$(CONFIG_EDAC_AXXIA_L3_6700) += axxia_edac-l3_56xx.o obj-$(CONFIG_EDAC_AXXIA_L2_CPU_5500) += axxia_edac-l2_cpu.o obj-$(CONFIG_EDAC_AXXIA_L2_CPU_5600) += axxia_edac-l2_cpu_56xx.o +obj-$(CONFIG_EDAC_AXXIA_L2_CPU_6700) += axxia_edac-l2_cpu_56xx.o obj-$(CONFIG_EDAC_GHES) += ghes_edac.o obj-$(CONFIG_EDAC_MCE_INJ) += mce_amd_inj.o diff --git a/drivers/edac/axxia_edac-cmc_56xx.c b/drivers/edac/axxia_edac-cmc_56xx.c index 3fc2af8..ccdd090 100644 --- a/drivers/edac/axxia_edac-cmc_56xx.c +++ b/drivers/edac/axxia_edac-cmc_56xx.c @@ -40,7 +40,13 @@ #define MPR_HDR2 "Lp. dram0 dram1" #define MPR_HDR4 " dram2 dram3" -#define INTEL_EDAC_MOD_STR "axxia56xx_edac" +#if defined(CONFIG_EDAC_AXXIA_CMEM_5600) +#define INTEL_EDAC_MOD_STR "axxia56xx_edac" +#endif + +#if defined(CONFIG_EDAC_AXXIA_CMEM_6700) +#define INTEL_EDAC_MOD_STR "axxia67xx_edac" +#endif #define AXI2_SER3_PHY_ADDR 0x008002c00000ULL #define AXI2_SER3_PHY_SIZE PAGE_SIZE diff --git a/drivers/edac/axxia_edac-l2_cpu_56xx.c b/drivers/edac/axxia_edac-l2_cpu_56xx.c index 8ddf018..e20ee10 100644 --- a/drivers/edac/axxia_edac-l2_cpu_56xx.c +++ b/drivers/edac/axxia_edac-l2_cpu_56xx.c @@ -30,7 +30,14 @@ #include "axxia_l2_56xx.h" +#if defined(CONFIG_EDAC_AXXIA_L2_CPU_5600) #define INTEL_EDAC_MOD_STR "axxia56xx_edac" +#endif + +#if defined(CONFIG_EDAC_AXXIA_L2_CPU_6700) +#define INTEL_EDAC_MOD_STR "axxia67xx_edac" +#endif + #define CORES_PER_CLUSTER 4 #define SYSCON_PERSIST_SCRATCH 0xdc @@ -268,9 +275,21 @@ static int intel_edac_l2_remove(struct platform_device *pdev) } static const struct of_device_id intel_edac_l2_match[] = { +#if defined(CONFIG_EDAC_AXXIA_L2_CPU_5600) + { .compatible = "intel,cortex-a57-l2-cache", }, + +#endif + +#if defined(CONFIG_EDAC_AXXIA_L2_CPU_6700) + + { + .compatible = "intel,cortex-a53-l2-cache", + }, + +#endif {}, }; @@ -283,9 +302,21 @@ static struct platform_driver intel_edac_l2_driver = { } }; static const struct of_device_id intel_edac_cpu_match[] = { +#if defined(CONFIG_EDAC_AXXIA_L2_CPU_5600) + { .compatible = "intel,cortex-a57-cpu", }, + +#endif + +#if defined(CONFIG_EDAC_AXXIA_L2_CPU_6700) + + { + .compatible = "intel,cortex-a53-cpu", + }, + +#endif {}, }; diff --git a/drivers/edac/axxia_edac-l3_56xx.c b/drivers/edac/axxia_edac-l3_56xx.c index 4fa9fe6..abf5e3a 100644 --- a/drivers/edac/axxia_edac-l3_56xx.c +++ b/drivers/edac/axxia_edac-l3_56xx.c @@ -2,12 +2,14 @@ * drivers/edac/axxia_edac-l3_56xx.c * * EDAC Driver for Intel's Axxia 5600 L3 (DICKENS) + * EDAC Driver for Intel's Axxia 6700 L3 (SHELLEY) * * Copyright (C) 2017 Intel Inc. * * This file may be distributed under the terms of the * GNU General Public License. */ +#define CREATE_TRACE_POINTS #include <linux/module.h> #include <linux/init.h> @@ -24,10 +26,21 @@ #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/arm-smccc.h> +#include <trace/events/edacl3.h> #include "edac_core.h" #include "edac_module.h" +#if defined(CONFIG_EDAC_AXXIA_L3_5600) #define INTEL_EDAC_MOD_STR "axxia56xx_edac" +#define CCN_XP_NODES 11 +#define CCN_HNI_NODES 1 +#endif + +#if defined(CONFIG_EDAC_AXXIA_L3_6700) +#define INTEL_EDAC_MOD_STR "axxia67xx_edac" +#define CCN_XP_NODES 18 +#define CCN_HNI_NODES 2 +#endif #define SYSCON_PERSIST_SCRATCH 0xdc #define L3_PERSIST_SCRATCH_BIT (0x1 << 4) @@ -55,7 +68,6 @@ #define CCN_HNI_NODE_BIT 8 #define CCN_HNF_NODES 8 -#define CCN_XP_NODES 11 #define CCN_DT_NODE_BASE_ADDR (1 * CCN_REGION_SIZE) #define CCN_HNI_NODE_BASE_ADDR(i) (0x80000 + (i) * CCN_REGION_SIZE) #define CCN_HNF_NODE_BASE_ADDR(i) (0x200000 + (i) * CCN_REGION_SIZE) @@ -151,7 +163,7 @@ struct intel_edac_dev_info { int irq_used; struct event_data data[CCN_HNF_NODES]; struct event_data data_xp[CCN_XP_NODES]; - struct event_data data_hni; + struct event_data data_hni[CCN_HNI_NODES]; struct regmap *syscon; void __iomem *dickens_L3; struct edac_device_ctl_info *edac_dev; @@ -233,6 +245,8 @@ static irqreturn_t ccn_irq_thread(int irq, void *device) __arm_smccc_smc(0xc4000027, CCN_MN_ERRINT_STATUS__INTREQ__DESSERT, 0, 0, &r); + trace_edacl3_smc_results(&r); + return IRQ_HANDLED; } @@ -262,24 +276,37 @@ static irqreturn_t ccn_irq_handler(int irq, void *device) err_or |= err_sig_val[i]; } - err_type_value[i] = readq(ccn_base + CCN_MN_ERROR_TYPE_VALUE); - err_type_value[i] = readq(ccn_base + CCN_MN_ERROR_TYPE_VALUE + 0x8); - err_type_value[i] = readq(ccn_base + CCN_MN_ERROR_TYPE_VALUE + 0x10); - err_type_value[i] = readq(ccn_base + CCN_MN_ERROR_TYPE_VALUE + 0x20); + trace_edacl3_sig_vals(err_sig_val[0], err_sig_val[1], + err_sig_val[2]); + + i = 0; + err_type_value[i] = readq(ccn_base + CCN_MN_ERROR_TYPE_VALUE); + err_type_value[++i] = readq(ccn_base + CCN_MN_ERROR_TYPE_VALUE + 0x8); + err_type_value[++i] = readq(ccn_base + CCN_MN_ERROR_TYPE_VALUE + 0x10); + err_type_value[++i] = readq(ccn_base + CCN_MN_ERROR_TYPE_VALUE + 0x20); + + trace_edacl3_error_types(err_type_value[0], err_type_value[1], + err_type_value[2], err_type_value[3]); /* check hni node */ - if ((0x1 << CCN_HNI_NODE_BIT) & err_sig_val[0]) { - err_synd_reg0 = readq(ccn_base + CCN_HNI_NODE_BASE_ADDR(0) + + for (i = 0; i < CCN_HNI_NODES; ++i) { + if ((0x1 << (CCN_HNI_NODE_BIT + i)) & err_sig_val[0]) { + err_synd_reg0 = readq(ccn_base + + CCN_HNI_NODE_BASE_ADDR(i) + CCN_NODE_ERR_SYND_REG0); - err_synd_reg1 = readq(ccn_base + CCN_HNI_NODE_BASE_ADDR(0) + + err_synd_reg1 = readq(ccn_base + + CCN_HNI_NODE_BASE_ADDR(i) + CCN_NODE_ERR_SYND_REG1); - dev_info->data_hni.err_synd_reg0 = err_synd_reg0; - dev_info->data_hni.err_synd_reg1 = err_synd_reg1; - dev_info->data_hni.idx = 0; + trace_edacl3_syndromes(err_synd_reg0, + err_synd_reg1); + dev_info->data_hni[i].err_synd_reg0 = err_synd_reg0; + dev_info->data_hni[i].err_synd_reg1 = err_synd_reg1; + dev_info->data_hni[i].idx = 0; - clear_node_error(ccn_base + CCN_HNI_NODE_BASE_ADDR(0) + - CCN_NODE_ERR_SYND_CLR); + clear_node_error(ccn_base + CCN_HNI_NODE_BASE_ADDR(i) + + CCN_NODE_ERR_SYND_CLR); + } } /* go through all hnf nodes */ @@ -293,6 +320,9 @@ static irqreturn_t ccn_irq_handler(int irq, void *device) CCN_HNF_NODE_BASE_ADDR(i) + CCN_NODE_ERR_SYND_REG1); + trace_edacl3_syndromes(err_synd_reg0, + err_synd_reg1); + dev_info->data[i].err_synd_reg0 = err_synd_reg0; dev_info->data[i].err_synd_reg1 = err_synd_reg1; dev_info->data[i].idx = i; @@ -313,6 +343,9 @@ static irqreturn_t ccn_irq_handler(int irq, void *device) dev_info->data_xp[i].err_synd_reg0 = err_synd_reg0; dev_info->data_xp[i].err_synd_reg1 = 0; + trace_edacl3_syndromes(err_synd_reg0, + err_synd_reg1); + clear_node_error(ccn_base + CCN_XP_NODE_BASE_ADDR(i) + CCN_NODE_ERR_SYND_CLR); } @@ -351,6 +384,9 @@ static void intel_l3_error_check(struct edac_device_ctl_info *edac_dev) err_syndrome_reg0.value = readq(addr + CCN_NODE_ERR_SYND_REG0); + + trace_edacl3_syndromes(err_syndrome_reg0.value, + (u64) 0); /* First error valid */ if (err_syndrome_reg0.reg0.first_err_vld) { if (err_syndrome_reg0.reg0.err_class & 0x3) { @@ -413,7 +449,7 @@ static int intel_edac_l3_probe(struct platform_device *pdev) dev_info->edac_dev = edac_device_alloc_ctl_info(0, dev_info->ctl_name, 1, dev_info->blk_name, - 8, 0, NULL, 0, + CCN_HNI_NODES, 0, NULL, 0, dev_info->edac_idx); if (!dev_info->edac_dev) { pr_info("No memory for edac device\n"); @@ -477,9 +513,21 @@ static int intel_edac_l3_remove(struct platform_device *pdev) } static const struct of_device_id intel_edac_l3_match[] = { +#if defined(CONFIG_EDAC_AXXIA_L2_CPU_5600) + { .compatible = "intel,ccn504-l3-cache", }, + +#endif + +#if defined(CONFIG_EDAC_AXXIA_L2_CPU_6700) + + { + .compatible = "intel,ccn512-l3-cache", + }, + +#endif {}, }; diff --git a/drivers/edac/axxia_edac-mc_56xx.c b/drivers/edac/axxia_edac-mc_56xx.c index 947f427..c1e13f5 100644 --- a/drivers/edac/axxia_edac-mc_56xx.c +++ b/drivers/edac/axxia_edac-mc_56xx.c @@ -43,7 +43,13 @@ #define MPR_HDR18 " dram9 dram10 dram11 dram12"\ " dram13 dram14 dram15 dram16 dram17" -#define INTEL_EDAC_MOD_STR "axxia56xx_edac" +#if defined(CONFIG_EDAC_AXXIA_SYSMEM_5600) +#define INTEL_EDAC_MOD_STR "axxia56xx_edac" +#endif + +#if defined(CONFIG_EDAC_AXXIA_SYSMEM_6700) +#define INTEL_EDAC_MOD_STR "axxia67xx_edac" +#endif #define AXI2_SER3_PHY_ADDR 0x008002c00000ULL #define AXI2_SER3_PHY_SIZE PAGE_SIZE diff --git a/drivers/misc/lsi-ncr.c b/drivers/misc/lsi-ncr.c index 769c511..2a8107d 100644 --- a/drivers/misc/lsi-ncr.c +++ b/drivers/misc/lsi-ncr.c @@ -174,8 +174,8 @@ ncr_register_write(const unsigned int value, unsigned int *address) if (0 == nca_big_endian) __raw_writel(value, address); - - __raw_writel(cpu_to_be32(value), address); + else + __raw_writel(cpu_to_be32(value), address); } /* diff --git a/include/trace/events/edacl3.h b/include/trace/events/edacl3.h new file mode 100644 index 0000000..5b63278 --- /dev/null +++ b/include/trace/events/edacl3.h @@ -0,0 +1,109 @@ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM edacl3 + +#if !defined(_TRACE_EDACL3_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_EDACL3_H + +#include <linux/types.h> +#include <linux/tracepoint.h> + + +TRACE_EVENT(edacl3_error_types, + TP_PROTO(u64 error_31_0, u64 error_63_32, + u64 error_95_64, u64 error_159_128), + + TP_ARGS(error_31_0, error_63_32, error_95_64, error_159_128), + + TP_STRUCT__entry( + __field(u64, error_31_0) + __field(u64, error_63_32) + __field(u64, error_95_64) + __field(u64, error_159_128) + ), + + TP_fast_assign( + __entry->error_31_0 = error_31_0; + __entry->error_63_32 = error_63_32; + __entry->error_95_64 = error_95_64; + __entry->error_159_128 = error_159_128; + ), + + TP_printk("Err types(0-3):(0x%016llx, 0x%016llx, 0x%016llx, 0x%016llx)", + (u64) __entry->error_31_0, (u64) __entry->error_63_32, + (u64) __entry->error_95_64, (u64) __entry->error_159_128 + ) +); + +TRACE_EVENT(edacl3_sig_vals, + TP_PROTO(u64 sig_val_63_0, u64 sig_val_127_64, u64 sig_val_191_128), + + TP_ARGS(sig_val_63_0, sig_val_127_64, sig_val_191_128), + + TP_STRUCT__entry( + __field(u64, sig_val_63_0) + __field(u64, sig_val_127_64) + __field(u64, sig_val_191_128) + ), + + TP_fast_assign( + __entry->sig_val_63_0 = sig_val_63_0; + __entry->sig_val_127_64 = sig_val_127_64; + __entry->sig_val_191_128 = sig_val_191_128; + ), + + TP_printk("Sig_val_regs(0-3):(0x%016llx, 0x%016llx, 0x%016llx)", + (u64) __entry->sig_val_63_0, (u64) __entry->sig_val_127_64, + (u64) __entry->sig_val_191_128 + ) +); + +TRACE_EVENT(edacl3_syndromes, + TP_PROTO(u64 syndrome0, u64 syndrome1), + + TP_ARGS(syndrome0, syndrome1), + + TP_STRUCT__entry( + __field(u64, syndrome0) + __field(u64, syndrome1) + ), + + TP_fast_assign( + __entry->syndrome0 = syndrome0; + __entry->syndrome1 = syndrome1; + ), + + TP_printk("Syndromes(0-1):(0x%016llx, 0x%016llx)", + (u64) __entry->syndrome0, (u64) __entry->syndrome1 + ) +); + + +TRACE_EVENT(edacl3_smc_results, + TP_PROTO(struct arm_smccc_res *ptr), + + TP_ARGS(ptr), + + TP_STRUCT__entry( + __field(u64, a0) + __field(u64, a1) + __field(u64, a2) + __field(u64, a3) + ), + + TP_fast_assign( + __entry->a0 = ptr->a0; + __entry->a1 = ptr->a1; + __entry->a2 = ptr->a2; + __entry->a3 = ptr->a3; + ), + + TP_printk("Smc(a0-a3):(0x%llx, 0x%llx, 0x%llx, 0x%llx)", + (u64) __entry->a0, (u64) __entry->a1, + (u64) __entry->a2, (u64) __entry->a3 + ) +); + +#endif /* _TRACE_EDACL3_H */ + +/* This part must be outside protection */ +#include <trace/define_trace.h> -- 2.7.4 -- _______________________________________________ linux-yocto mailing list linux-yocto@yoctoproject.org https://lists.yoctoproject.org/listinfo/linux-yocto