From: John Jacques <john.jacq...@intel.com>
Make sure everything gets put back to normal when the
speed changes from Gen1 to Gen2/Gen3.
Signed-off-by: John Jacques <john.jacq...@intel.com>
---
drivers/pci/host/pcie-axxia.c | 55 ++++++++++++++++++++++---------------------
1 file changed, 28 insertions(+), 27 deletions(-)
diff --git a/drivers/pci/host/pcie-axxia.c b/drivers/pci/host/pcie-axxia.c
index 1859246..0eee0b0 100644
--- a/drivers/pci/host/pcie-axxia.c
+++ b/drivers/pci/host/pcie-axxia.c
@@ -905,10 +905,10 @@ axxia_pcie_los_wa(struct pcie_port *pp, unsigned int
max_width)
int max_target;
unsigned int lane0_dig_asic_rx_asic_in_0;
unsigned int lane0_dig_asic_rx_asic_out_0;
- unsigned int lane0_idg_asic_rx_ovrd_in_0;
+ unsigned int lane0_dig_asic_rx_ovrd_in_0;
unsigned int lane1_dig_asic_rx_asic_in_0;
unsigned int lane1_dig_asic_rx_asic_out_0;
- unsigned int lane1_idg_asic_rx_ovrd_in_0;
+ unsigned int lane1_dig_asic_rx_ovrd_in_0;
if (0 == axxia_pei_is_control_set())
return -1;
@@ -1059,18 +1059,18 @@ axxia_pcie_los_wa(struct pcie_port *pp, unsigned int
max_width)
max_target = 4;
lane0_dig_asic_rx_asic_in_0 = 0x2022;
lane0_dig_asic_rx_asic_out_0 = 0x202e;
- lane0_idg_asic_rx_ovrd_in_0 = 0x200a;
+ lane0_dig_asic_rx_ovrd_in_0 = 0x200a;
lane1_dig_asic_rx_asic_in_0 = 0x2222;
lane1_dig_asic_rx_asic_out_0 = 0x222e;
- lane1_idg_asic_rx_ovrd_in_0 = 0x220a;
+ lane1_dig_asic_rx_ovrd_in_0 = 0x220a;
} else {
max_target = 1;
lane0_dig_asic_rx_asic_in_0 = 0x4044;
lane0_dig_asic_rx_asic_out_0 = 0x405c;
- lane0_idg_asic_rx_ovrd_in_0 = 0x4014;
+ lane0_dig_asic_rx_ovrd_in_0 = 0x4014;
lane1_dig_asic_rx_asic_in_0 = 0x4444;
lane1_dig_asic_rx_asic_out_0 = 0x445c;
- lane1_idg_asic_rx_ovrd_in_0 = 0x4414;
+ lane1_dig_asic_rx_ovrd_in_0 = 0x4414;
}
do_gettimeofday(&start);
@@ -1078,6 +1078,7 @@ axxia_pcie_los_wa(struct pcie_port *pp, unsigned int
max_width)
for (;;) {
int i;
unsigned short temp;
+ unsigned int region;
/*
* In all cases (see the initialization of lane_mask
@@ -1089,41 +1090,41 @@ axxia_pcie_los_wa(struct pcie_port *pp, unsigned int
max_width)
if (0 == (lane_mask & (0xff << ((i - 1) * 8))))
continue;
- ncr_read(NCP_REGION_ID(0x115, i),
- lane0_dig_asic_rx_asic_in_0, 2, &temp);
+ region = NCP_REGION_ID(0x115, i);
+ ncr_read(region, lane0_dig_asic_rx_asic_in_0, 2, &temp);
if (2 == ((temp & 0x180) >> 7)) {
- ncr_read(NCP_REGION_ID(0x115, i),
- lane0_dig_asic_rx_asic_out_0,
+ ncr_read(region, lane0_dig_asic_rx_asic_out_0,
2, &temp);
- if (0 != (temp & 2))
+ if (0 != (temp & 2)) {
temp = 0x4700;
- else
+ ncr_write(region,
+ lane0_dig_asic_rx_ovrd_in_0,
+ 2, &temp);
temp = 0x0700;
-
- ncr_write(NCP_REGION_ID(0x115, i),
- lane0_idg_asic_rx_ovrd_in_0,
- 2, &temp);
+ ncr_write(region,
+ lane0_dig_asic_rx_ovrd_in_0,
+ 2, &temp);
+ }
}
- ncr_read(NCP_REGION_ID(0x115, i),
- lane1_dig_asic_rx_asic_in_0,
- 2, &temp);
+ ncr_read(region, lane1_dig_asic_rx_asic_in_0, 2, &temp);
if (2 == ((temp & 0x180) >> 7)) {
- ncr_read(NCP_REGION_ID(0x115, i),
- lane1_dig_asic_rx_asic_out_0,
+ ncr_read(region, lane1_dig_asic_rx_asic_out_0,
2, &temp);
- if (0 != (temp & 2))
+ if (0 != (temp & 2)) {
temp = 0x4700;
- else
+ ncr_write(region,
+ lane1_dig_asic_rx_ovrd_in_0,
+ 2, &temp);
temp = 0x0700;
-
- ncr_write(NCP_REGION_ID(0x115, i),
- lane1_idg_asic_rx_ovrd_in_0,
- 2, &temp);
+ ncr_write(region,
+ lane1_dig_asic_rx_ovrd_in_0,
+ 2, &temp);
+ }
}
}
--
2.7.4
--
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