From: Rodrigo Vivi <rodrigo.v...@intel.com>
commit 938361e7a50619b76a1415c86438eaee41397220 upstream.
Panel Power sequences for CNP is similar to Broxton,
but with only one sequencer.
Main difference from SPT is that PP_DIVISOR was removed
and power cycle delay has been moved to PP_CONTROL.
v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
as on Broxton. (Found by DK)
v3: Improve commit message. (By DK)
Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.tay...@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
Link:
http://patchwork.freedesktop.org/patch/msgid/1496434004-29812-6-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song <liwei.song.ls...@gmail.com>
---
drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8a883e9abedd..93075873bb2f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -754,7 +754,7 @@ static void intel_pps_get_registers(struct drm_i915_private
*dev_priv,
regs->pp_stat = PP_STATUS(pps_idx);
regs->pp_on = PP_ON_DELAYS(pps_idx);
regs->pp_off = PP_OFF_DELAYS(pps_idx);
- if (!IS_GEN9_LP(dev_priv))
+ if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
regs->pp_div = PP_DIVISOR(pps_idx);
}
@@ -5150,7 +5150,7 @@ intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv,
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
- if (!IS_GEN9_LP(dev_priv)) {
+ if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
I915_WRITE(regs.pp_ctrl, pp_ctl);
pp_div = I915_READ(regs.pp_div);
}
@@ -5168,7 +5168,7 @@ intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv,
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
PANEL_POWER_DOWN_DELAY_SHIFT;
- if (IS_GEN9_LP(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT;
if (tmp > 0)
@@ -5325,7 +5325,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
* formula. */
- if (IS_GEN9_LP(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5351,7 +5351,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
- if (IS_GEN9_LP(dev_priv))
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
I915_WRITE(regs.pp_ctrl, pp_div);
else
I915_WRITE(regs.pp_div, pp_div);
@@ -5359,7 +5359,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x,
PP_OFF %#x, PP_DIV %#x\n",
I915_READ(regs.pp_on),
I915_READ(regs.pp_off),
- IS_GEN9_LP(dev_priv) ?
+ (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
(I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
I915_READ(regs.pp_div));
}
--
2.7.4
--
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