From: Limeng <meng...@windriver.com>
Add a overlay to implement updating FPGA congifure in Linux
enviroment in real time via Stratix 10 FPGA manager.
Signed-off-by: Meng Li <meng...@windriver.com>
---
arch/arm64/boot/dts/altera/Makefile | 2 +-
.../dts/altera/socfpga_stratix10_fpga_update.dts | 17 +++++++++++++++++
2 files changed, 18 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts
diff --git a/arch/arm64/boot/dts/altera/Makefile
b/arch/arm64/boot/dts/altera/Makefile
index 5b08e85..ecc0560 100644
--- a/arch/arm64/boot/dts/altera/Makefile
+++ b/arch/arm64/boot/dts/altera/Makefile
@@ -1,4 +1,4 @@
-dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb
+dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb
socfpga_stratix10_fpga_update.dtb
dtb-$(CONFIG_ARCH_STRATIX10SWVP) += stratix10_swvp.dtb
always := $(dtb-y)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts
b/arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts
new file mode 100644
index 0000000..c7811cc
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts
@@ -0,0 +1,17 @@
+/dts-v1/;
+/plugin/;
+/ {
+ fragment@0 {
+ target-path = "/soc/base_fpga_region";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ firmware-name = "soc_s10_fpga_config.rbf";
+ config-complete-timeout-us = <2000000>;
+ };
+ };
+};
+
--
1.7.9.5
--
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