The hardwaremain become more tidy. How about the progress about the romcc? I hope I can enable debug info while include all ati support stuff.
Regards YH -----邮件原件----- 发件人: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] 发送时间: 2004年7月7日 21:03 收件人: LinuxBIOS 抄送: YhLu; ron minnich; Stefan Reinauer 主题: Re: CPU refactoring status.... [EMAIL PROTECTED] (Eric W. Biederman) writes: > The next big task is to get make the SMP cpu initialization methods > normal device tree methods. I have everything ready to do that > except I need a good way to get the information in the struct > mem_range array by sizeram(). My gut feel is that I want to > incorporate the sizeram functionality into the resource allocator, Moving sizeram into read_resources/set_resources comes out fairly clean, but it did require some grunt work. That has allowed me to sort out the device tree and have a fairly generic method of initializing cpus. Cpus don't fit into device model methods as nicely as I would like (largely because their methods have to run on the cpu in question). But it does work well enough I can remove the special case from hardwaremain. I still have a special case in the root_device methods but that can be overridden, if necessary. Because I have restructured where things fall in the device tree. Because I have removed the sizeram call. Because I have refactored x86 cpu handling. Because I have removed the array initial_apic_id. Every port in the tree is likely to break when I check this code in. I have the arima/hdama working and I can with a little care fix up the k8 based ports. I can also likely fixup the recent e7501 forward port from the freebios tree. However beyond that I don't have testing resources to fix things up so I am looking for some feedback before I break everything. When in the next week or so is a good time? Does any one have concerns about this set of changes? I have attached my current version of hardwaremain below to give a feel of what the changes look like. Ok now I am off to bed. Before I commit anything I am going to let the code sit a little. Good Night, Eric /* * C Bootstrap code for the LinuxBIOS */ #include <console/console.h> #include <mem.h> #include <version.h> #include <boot/tables.h> #include <device/device.h> #include <device/pci.h> #include <device/chip.h> #include <delay.h> #include <stdlib.h> #include <part/hard_reset.h> #include <boot/elf.h> void hardwaremain(int boot_complete) { /* the order here is a bit tricky. We don't want to do much of * anything that uses config registers until after PciAllocateResources * since that function also figures out what kind of config strategy * to use (type 1 or type 2). * so we turn on cache, then worry about PCI setup, then do other * things, so that the other work can use the PciRead* and PciWrite* * functions. */ struct lb_memory *lb_mem; post_code(0x80); CONFIGURE(CONF_PASS_PRE_CONSOLE); /* displayinit MUST PRECEDE ALL PRINTK! */ console_init(); post_code(0x39); printk_notice("LinuxBIOS-%s%s %s %s...\n", linuxbios_version, linuxbios_extra_version, linuxbios_build, (boot_complete)?"rebooting":"booting"); post_code(0x40); /* If we have already booted attempt a hard reboot */ if (boot_complete) { hard_reset(); } init_timer(); /* needs to be moved into static configuration */ CONFIGURE(CONF_PASS_PRE_PCI); /* pick how to scan the bus. This is first so we can get at memory size. */ printk_info("Finding PCI configuration type.\n"); pci_set_method(); post_code(0x5f); enumerate_static_devices(); dev_enumerate(); post_code(0x66); /* Now do the real bus. * We round the total ram up a lot for thing like the SISFB, which * shares high memory with the CPU. */ dev_configure(); post_code(0x88); dev_enable(); dev_initialize(); post_code(0x89); CONFIGURE(CONF_PASS_POST_PCI); /* Now that we have collected all of our information * write our configuration tables. */ lb_mem = write_tables(); CONFIGURE(CONF_PASS_PRE_BOOT); elfboot(lb_mem); } _______________________________________________ Linuxbios mailing list [EMAIL PROTECTED] http://www.clustermatic.org/mailman/listinfo/linuxbios
