Repeat the i2c address two times make the memory modules fail. At that case
some thing being done twice...cause that...
YH
-----Original Message-----
From: YhLu
Sent: Wednesday, November 24, 2004 10:44 AM
To: [EMAIL PROTECTED]
Cc: Stefan Reinauer; 'LinuxBIOS'
Subject: RE: 4G 4 Rank memory module
Eric,
Our MB all CS are connected.
DIMM0 and DIMM1 are using 0, 1, 4, 5.
DIMM2 and DIMM3 are using 2, 3, 6, 7.
Then need to change to
static const struct mem_controller cpu[] = {
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, (0xa<<3)|0, (0xa<<3)|2, },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, (0xa<<3)|1, (0xa<<3)|3, },
},
Regards
YH
-----Original Message-----
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
Sent: Wednesday, November 24, 2004 12:55 AM
To: YhLu
Cc: Stefan Reinauer; 'LinuxBIOS'
Subject: Re: 4G 4 Rank memory module
YhLu <[EMAIL PROTECTED]> writes:
> It can treat 4G as 2G modules, if I comment out physical bank check. (!=2
> get out).
Ah so it is the explicit check for <= 2 Ranks that is the immediate problem
:)
This case is peculiar enough I did not add support because I could not test
it.
Does your board have 4 chip selects running to the dimm socket?
If not you cannot support 4 rank dimms.
What does your struct mem_controller look like?
One partial solution would be to simply repeat the spd address
twice in the channel structure, and comment out the maximum bank check.
Of course that would fail for non quad rank dimms.
So I am not quite certain what the complete solution is. YhLu once you
describe
how your dimm sockets are wired we can figure something out.
static const struct mem_controller cpu[] = {
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
},
Eric
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