"Eric W. Biederman" wrote:
>
> Basically document number 21656 Athlon Process BIOS Software & debug
> developers guide. Has all of that except my chapter 4 on processor
> caches, that basically says nothing. I get the impression that for
> the slot Athlons you need to do something but for the socket
> processors you really don't. There is a changlog entry that says they
> removed much of the discussion on L2 init.
>
> So I feel like I should have what I need but it isn't there.
>
> If it wasn't for your earlier comment about not having L2 cache init
> I would assume the socket athlons were like the socket athlons and
> nothing actually needs to be done.
>
> Eric
Appreantly we have two different verions of the same document (at least
the same number 21656). In my document the whole Chpater 6 is talking
about L2 cache init. and Chapter 9 talks about K7 specific MSR. You
will never get L2 right without this information.
BTW, I don't think that you don't have to program anything to init L2
for
Socket A Athlons. My Duron 600 shown in Extreme Linux is an example.
Ollie
