I would still like to know about raminit.inc, it seems to be very similar with l440gx/raminit.inc. Some of the registers used in E7500/raminit.inc are not even valid registers as per the E7500 MCH spec.
Just an observation, maybe I am missing something, Balbir | |Ronald G Minnich <[EMAIL PROTECTED]> writes: | |> I'm not looking at that code until next week :-) |> |> but I am pretty sure the startup code in E7500 is all in C, |see Eric's |> oh-so-fine cache-as-ram hack. | |The LinuxBIOS tree is significantly behind my current tree. |Once I get a chance to breath, or someone yelps loud enough, I |will push the current changes back into LinuxBIOS CVS. | |We prototyped with the cache-as-ram trick. But given the current |major P4 architecture instability, it was decided to do the |good version in assembly. cache-as-ram where there isn't |explict architecture support of the idea, requires |unpredictable amounts |of maintenance. And when a new processor comes out the last |thing you want to do is make all of your old code work again. | |Eric |
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