Hi
after a few months of work we (my mentor Mondrian Nuessle and me)
managed to get Iwill DK8HTX board running.
Porting LinuxBIOS to "DK8HTX" was part of an academic project. Main
goal was to get the htx socket running together with our htx fpga
board:
http://hypertransport.org/products/productdetail.cfm?RecordID=75
Right now we have all on-board devices working. Even xorg shows up. Only
exception is native vga-bios. It gets loaded but just a few lines of LB-boot
are printed. Anyway at least our HTX adaptor card is working :)
We also plan to contribute to the LB-Project by offering a walk
through / tutorial that should explain step by step how to get LB
running with DK8HTX.
thx, for all your help! LinuxBIOS is great :).
Phil
-----------------------------------
Computer Architecture Group
University of Mannheim
> YH,
>
> Thanks for the suggestion. I decreased LOG level to 8, and did not see
> "IDE1 IDE0 PCI: 00:07.1 init" in the LOG. Then I hacked amd8111_ide.c
> now I see "IDE1 IDE0 PCI: *01:04.3* init" in the log. And still the IDE
> timeout happens in FILO... but this is not suprising since it looks like
> the wrong PCI address is assigned to IDE(?) If so, do you know how to
> correct this?
>
> Thanks,
> Chris
>
> > Please decrease that LOG level to 8.
> >
> > And you should got
> > PCI:00:07.1 init
> > IDE1
> > IDE0
> >
> > in your log output.
> >
> > If it still doesn't work, hardcode amd8111_ide.c to enable ide device
> > directly.
> >
> > YH
> >
> > -----Original Message-----
> > From: Chris Stillo [mailto:[EMAIL PROTECTED]
> > Sent: Thursday, September 21, 2006 3:57 PM
> > To: Lu, Yinghai
> > Cc: [email protected]; Stefan Reinauer
> > Subject: Re: [LinuxBIOS] DK8-HTX FILO IDE timeout
> >
> > I added these lines and recompiled, but it still does not work. Maybe
> > there is still something else missing? I will re-check PCI configuration
> >
> > in MB's Config.lb, must still be an error in there...
> >
> >> Check serengeti_leopard or tyan/s2881 etc MB Config.lb to add two
> >
> > lines
> >
> >> to enable your IDE devices.
> >>
> >> YH
> >>
> >> -----Original Message-----
> >> From: Chris Stillo [mailto:[EMAIL PROTECTED]
> >> Sent: Thursday, September 21, 2006 3:24 PM
> >> To: Lu, Yinghai
> >> Cc: [email protected]; Stefan Reinauer
> >> Subject: Re: [LinuxBIOS] DK8-HTX FILO IDE timeout
> >>
> >> No, those lines are not there in MB Config... I serach for 'ide0' and
> >> find nothing... where exactly do they go in the file?
> >>
> >>> Please check if you have register "ide0_enable"="1" in MB Config.lb
> >>>
> >>> chip southbridge/amd/amd8111
> >>> # this "device pci 0.0" is the parent the next
> >
> > one
> >
> >>> # PCI bridge
> >>> device pci 0.0 on
> >>> device pci 0.0 on end
> >>> device pci 0.1 on end
> >>> device pci 0.2 on end
> >>> device pci 1.0 off end
> >>> end
> >>> .....
> >>> register "ide0_enable"="1"
> >>> register "ide1_enable"="1"
> >>>
> >>> ....
> >>>
> >>>
> >>> YH
> >>>
> >>>
> >>> -----Original Message-----
> >>> From: Chris Stillo [mailto:[EMAIL PROTECTED]
> >>> Sent: Thursday, September 21, 2006 3:13 PM
> >>> To: Lu, Yinghai
> >>> Cc: [email protected]; Stefan Reinauer
> >>> Subject: Re: [LinuxBIOS] DK8-HTX FILO IDE timeout
> >>>
> >>> Hi YH,
> >>>
> >>> I checked MB Config.lb as you suggested. From lspci I know my IDE
> >>> controller is here:
> >>>
> >>> 00:07.1 IDE interface: Advanced Micro Devices [AMD] AMD-8111 IDE (rev
> >>> 03)
> >>>
> >>> Yet I do not see 00:07.1 mentioned in the MB Config.lb in the
> >>> southbridge section. Maybe this is the issue... , maybe IDE is not
> >>> configured since SATA would be mostly used? (My SATA drive is
> >>> recognized, but has XP on it :| -- it is presenlty disconnected).
> >>>
> >>> I also included AMD 3111 chip.h below, which looks ok. I have not
> >>> modified either file at all.
> >>> If you see an error please let me know...
> >>>
> >>> Thanks,
> >>> Chris
> >>>
> >>>> Check your MB Config.lb to see if amd8111 is under correct 0.18.0
> >>>
> >>> link.
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>
> >>> # config for Iwill/DK8HTX
> >>> chip northbridge/amd/amdk8/root_complex
> >>> device pci_domain 0 on
> >>> chip northbridge/amd/amdk8
> >>> device pci 18.0 on # LDT 0
> >>> chip southbridge/amd/amd8131
> >>> device pci 0.0 on end
> >>> device pci 0.1 on end
> >>> device pci 1.0 on end
> >>> device pci 1.1 on end
> >>> end
> >>> chip southbridge/amd/amd8111
> >>> # this "device pci 0.0" is the parent the next
> >
> > one
> >
> >>> # PCI bridge
> >>> device pci 0.0 on
> >>> device pci 0.0 on end
> >>> device pci 0.1 on end
> >>> device pci 0.2 on end
> >>> device pci 1.0 off end
> >>> end
> >
> > ------------------------------------------------------------------------
> >
> >>> -------------------------------
> >>>
> >>> /LinuxBIOSv2/src/southbridge/amd/amd8111
> >>> bash-3.1$ more chip.h
> >>>
> >>> #ifndef AMD8111_CHIP_H
> >>> #define AMD8111_CHIP_H
> >>>
> >>> struct southbridge_amd_amd8111_config
> >>> {
> >>> unsigned int ide0_enable : 1;
> >>> unsigned int ide1_enable : 1;
> >>> unsigned int phy_lowreset : 1;
> >>> };
> >>>
> >>> struct chip_operations;
> >>> extern struct chip_operations southbridge_amd_amd8111_ops;
> >>>
> >>> #endif /* AMD8111_CHIP_H */
> >>>
> >>>> YH
>
diff -U 3 -H -d -r -N -x .svn -- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/Config.lb LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/Config.lb
--- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/Config.lb 2006-09-27 16:15:25.000000000 +0200
+++ LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/Config.lb 2006-09-27 14:58:22.000000000 +0200
@@ -43,12 +43,19 @@
##
driver mainboard.o
+
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
+## SI Sata 3114 driver
+dir /drivers/si/3114
+
## ATI Rage XL framebuffering graphics driver
-dir /drivers/ati/ragexl
+if CONFIG_CONSOLE_BTEXT dir /drivers/ati/ragexl end
+
+## Support for winbond chip
+dir /superio/winbond/w83627hf
##
## Romcc output
@@ -132,9 +139,25 @@
# config for Iwill/DK8HTX
chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # LDT 0
+ # HTX socket
+ device pci 0.0 on end
+ device pci 1.0 on end
+ end # LDT0
+ device pci 18.0 on # LDT 1
+ # no devices at the moment
+ end # LDT1
+ device pci 18.0 on # LDT 2
chip southbridge/amd/amd8131
device pci 0.0 on end
device pci 0.1 on end
@@ -147,22 +170,27 @@
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
- device pci 0.2 on end
+ device pci 0.2 off end
device pci 1.0 off end
+ chip drivers/pci/onboard
+ device pci 6.0 on end
+ register "rom_address" = "0xfff80000"
+ end
end
device pci 1.0 on
chip superio/winbond/w83627hf
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
+
+ io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
+ io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
@@ -170,14 +198,19 @@
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
- device pnp 2e.8 off end # GPIO2
+ device pnp 2e.8 on # GPIO2
+ io 0x07 = 0x08ff
+ io 0x30 = 0x01ff
+ io 0x2b = 0xd0ff
+ io 0xf0 = 0xef16
+ end
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
@@ -192,11 +225,11 @@
device pci 1.2 on end
device pci 1.3 on end
device pci 1.5 off end
- device pci 1.6 off end
+ device pci 1.6 off end # modem
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
end
- end # LDT0
- device pci 18.0 on end # LDT1
- device pci 18.0 on end # LDT2
+ end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
@@ -210,13 +243,5 @@
device pci 19.3 on end
end
end
- device apic_cluster 0 on
- chip cpu/amd/socket_940
- device apic 0 on end
- end
- chip cpu/amd/socket_940
- device apic 1 on end
- end
- end
end
diff -U 3 -H -d -r -N -x .svn -- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/Options.lb LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/Options.lb
--- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/Options.lb 2006-09-27 16:15:25.000000000 +0200
+++ LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/Options.lb 2006-09-27 15:30:28.000000000 +0200
@@ -47,11 +47,18 @@
uses CC
uses HOSTCC
uses OBJCOPY
-
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_CONSOLE_BTEXT
uses CONFIG_USE_INIT
+uses CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
+uses K8_HW_MEM_HOLE_SIZEK
+uses CONFIG_CHIP_NAME
+uses K8_SB_HT_CHAIN_ON_BUS0
+
## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
+default ROM_SIZE=(512*1024)
###
### Build options
@@ -104,6 +111,17 @@
default CONFIG_MAX_CPUS=2
default CONFIG_MAX_PHYSICAL_CPUS=2
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
+#1G memory hole
+default K8_HW_MEM_HOLE_SIZEK=0x100000
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=0
+default CONFIG_PCI_ROM_RUN=0
+
+
##
## Build code to setup a generic IOAPIC
##
@@ -112,8 +130,8 @@
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="HDAMA"
-default MAINBOARD_VENDOR="ARIMA"
+default MAINBOARD_PART_NUMBER="DK8HTX"
+default MAINBOARD_VENDOR="IWILL"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
@@ -211,5 +229,7 @@
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default K8_SB_HT_CHAIN_ON_BUS0=0
+
### End Options.lb
end
diff -U 3 -H -d -r -N -x .svn -- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/auto.c
--- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c 2006-09-27 16:15:25.000000000 +0200
+++ LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/auto.c 2006-08-22 14:32:19.000000000 +0200
@@ -71,49 +71,6 @@
}
}
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
- /* Routing Table Node i
- *
- * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
- * i: 0, 1, 2, 3, 4, 5, 6, 7
- *
- * [ 0: 3] Request Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [11: 8] Response Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [19:16] Broadcast route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- */
-
- uint32_t ret=0x00010101; /* default row entry */
-
- static const unsigned int rows_2p[2][2] = {
- { 0x00050101, 0x00010404 },
- { 0x00010404, 0x00050101 }
- };
-
- if(maxnodes>2) {
- print_debug("this mainboard is only designed for 2 cpus\r\n");
- maxnodes=2;
- }
-
- if (!(node>=maxnodes || row>=maxnodes)) {
- ret=rows_2p[node][row];
- }
-
- return ret;
-}
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@@ -178,7 +135,7 @@
print_err("B\n");
needs_reset = setup_coherent_ht_domain();
print_err("C\n");
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+ needs_reset |= ht_setup_chains_x();
print_err("D\n");
if (needs_reset) {
print_info("ht reset -\r\n");
@@ -211,4 +168,5 @@
print_err("J\n");
#endif
print_err("K\n");
+
}
diff -U 3 -H -d -r -N -x .svn -- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/irq_tables.c LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/irq_tables.c
--- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/irq_tables.c 2006-09-27 16:15:25.000000000 +0200
+++ LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/irq_tables.c 2006-08-28 18:55:16.000000000 +0200
@@ -8,33 +8,34 @@
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
- 32+16*12, /* there can be total 12 devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
+ 32+16*12, /* there can be total 12 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
(0x07<<3)|0x3, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x1022, /* Vendor */
- 0x746b, /* Device */
- 0, /* Crap (miniport) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x1022, /* Vendor */
+ 0x746b, /* Device */
+ 0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x6d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ 0x51, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x07<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x0, 0x0},
- {0x03,(0x00<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0x0def8}}, 0x0, 0x0},
- {0x02,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x1, 0x0},
- {0x02,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x2, 0x0},
- {0x01,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x3, 0x0},
- {0x01,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x4, 0x0},
- {0x03,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x5, 0x0},
- {0x03,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x6, 0x0},
- {0x03,(0x06<<3)|0x0, {{0x03, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x02,(0x03<<3)|0x0, {{0x04, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x02,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x02,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x0, 0x0},
+ {0x01,(0x00<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0x0def8}}, 0x0, 0x0},
+ {0xff,(0x01<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x03, 0xdef8}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x03,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x1, 0x0},
+ {0x03,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x2, 0x0},
+ {0x03,(0x03<<3)|0x0, {{0x04, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x03,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x03,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x02,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
+ {0x01,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x4, 0x0},
+ {0x01,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x5, 0x0},
+ {0x01,(0x06<<3)|0x0, {{0x03, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
}
};
+
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
diff -U 3 -H -d -r -N -x .svn -- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/mptable.c LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/mptable.c
--- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/mptable.c 2006-09-27 16:15:25.000000000 +0200
+++ LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/mptable.c 2006-08-28 18:44:50.000000000 +0200
@@ -39,20 +39,21 @@
device_t dev;
/* 8111 */
- dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
+ dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
+ printk_err("Found PCI bus at %d and ISA Bus at %d\n",bus_8111_1,bus_isa);
}
else {
- printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+ printk_err("ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_1 = 4;
bus_isa = 5;
}
/* 8131-1 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
+ dev = dev_find_slot(0, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
@@ -63,7 +64,7 @@
bus_8131_1 = 2;
}
/* 8131-2 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
+ dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
@@ -87,7 +88,7 @@
device_t dev;
struct resource *res;
/* 8131 apic 3 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
+ dev = dev_find_slot(0, PCI_DEVFN(0x01,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
@@ -95,7 +96,7 @@
}
}
/* 8131 apic 4 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
+ dev = dev_find_slot(0, PCI_DEVFN(0x02,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
@@ -105,6 +106,7 @@
}
/* ISA backward compatibility interrupts */
+ /* mp_config_table, irqtype, irqflag, srcbus, srcbusirq, dstapic, dstirq */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, 0x02, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
@@ -115,20 +117,20 @@
bus_isa, 0x03, 0x02, 0x03);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x04, 0x02, 0x04);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x05, 0x02, 0x05);
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_isa, 0x05, 0x02, 0x05); */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x06, 0x02, 0x06);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x07, 0x02, 0x07);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, /* active_hi, edge */
bus_isa, 0x08, 0x02, 0x08);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x09, 0x02, 0x09);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0a, 0x02, 0x0a);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0b, 0x02, 0x0b);
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_isa, 0x09, 0x02, 0x09); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_isa, 0x0a, 0x02, 0x0a); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_isa, 0x0b, 0x02, 0x0b); */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0c, 0x02, 0x0c);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
@@ -145,58 +147,59 @@
bus_isa, 0x00, MP_APIC_ALL, 0x01);
- /* PCI Slot 1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|3, 0x02, 0x10);
+/* /\* PCI Slot 1 *\/ */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_2, (1<<2)|0, 0x02, 0x11); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_2, (1<<2)|1, 0x02, 0x12); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_2, (1<<2)|2, 0x02, 0x13); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_2, (1<<2)|3, 0x02, 0x10); */
- /* PCI Slot 2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|0, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|1, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|2, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|3, 0x02, 0x11);
+/* /\* PCI Slot 2 *\/ */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_2, (2<<2)|0, 0x02, 0x12); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_2, (2<<2)|1, 0x02, 0x13); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_2, (2<<2)|2, 0x02, 0x10); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_2, (2<<2)|3, 0x02, 0x11); */
- /* PCI Slot 3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|3, 0x02, 0x10);
+/* /\* PCI Slot 3 *\/ */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_1, (1<<2)|0, 0x02, 0x11); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_1, (1<<2)|1, 0x02, 0x12); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_1, (1<<2)|2, 0x02, 0x13); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_1, (1<<2)|3, 0x02, 0x10); */
- /* PCI Slot 4 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|0, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|1, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|2, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|3, 0x02, 0x11);
+/* /\* PCI Slot 4 *\/ */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_1, (2<<2)|0, 0x02, 0x12); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_1, (2<<2)|1, 0x02, 0x13); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_1, (2<<2)|2, 0x02, 0x10); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8131_1, (2<<2)|3, 0x02, 0x11); */
- /* PCI Slot 5 */
-#warning "FIXME get the irqs right, it's just hacked to work for now"
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|3, 0x02, 0x10);
+/* /\* PCI Slot 5 *\/ */
+/* #warning "FIXME get the irqs right, it's just hacked to work for now" */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8111_1, (5<<2)|0, 0x02, 0x11); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8111_1, (5<<2)|1, 0x02, 0x12); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8111_1, (5<<2)|2, 0x02, 0x13); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, */
+/* bus_8111_1, (5<<2)|3, 0x02, 0x10); */
/* PCI Slot 6 */
+ /* mp_config_table, irqtype, irqflag, srcbus, srcbusirq, dstapic, dstirq */
#warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|0, 0x02, 0x10);
@@ -207,18 +210,31 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|3, 0x02, 0x13);
+ /* onboard USB */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_8111_1, (0<2)|3, 0x02, 0x13);
+
+ /* on board VGA */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_8111_1, (6<<2)|1, 0x02, 0x12);
+
/* On board nics */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (3<<2)|0, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (4<<2)|0, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_8131_1, (3<<2)|0, 0x03, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_8131_1, (4<<2)|0, 0x03, 0x0);
+
+ /* On board Sata */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_8131_1, (5<<2)|0, 0x03, 0x1);
+
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
- printk_debug("Wrote the mp table end at: %p - %p\n",
+ printk_err("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
diff -U 3 -H -d -r -N -x .svn -- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/resourcemap.c LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/resourcemap.c
--- LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/resourcemap.c 2006-09-27 16:15:25.000000000 +0200
+++ LinuxBIOSv2_final/src/mainboard/Iwill/DK8HTX/resourcemap.c 2006-08-10 11:32:05.000000000 +0200
@@ -183,7 +183,7 @@
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000c020,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00010000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -213,7 +213,7 @@
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00009033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x0000d003,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
diff -U 3 -H -d -r -N -x .svn -- LinuxBIOSv2/targets/Iwill/dk8htx/Config.lb LinuxBIOSv2_final/targets/Iwill/dk8htx/Config.lb
--- LinuxBIOSv2/targets/Iwill/dk8htx/Config.lb 2006-09-27 16:17:15.000000000 +0200
+++ LinuxBIOSv2_final/targets/Iwill/dk8htx/Config.lb 2006-09-27 15:31:09.000000000 +0200
@@ -1,43 +1,80 @@
# Sample config file for
-# the Iwill DK8S2
-# This will make a target directory of ./dk8s2
+# the Iwill DK8HTX
+# This will make a target directory of ./dk8htx
target dk8htx
-
mainboard Iwill/DK8HTX
-option HAVE_HARD_RESET=1
+###
+### Set boot behavior
+###
+# option HAVE_HARD_RESET = 1
+# option HAVE_FALLBACK_BOOT = 1
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
-option ROM_SIZE=512*1024
-option HAVE_FALLBACK_BOOT=1
-
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
+###
+### mptable support
+###
+# option HAVE_OPTION_TABLE = 1
+# option HAVE_MP_TABLE = 1
-#
###
### Build code to export a programmable irq routing table
###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=12
-#
+# option HAVE_PIRQ_TABLE = 1
+# option IRQ_SLOT_COUNT = 9
+
+
+###
+### Image Options
+###
+## Compute ROM Size
+## reserve 32k for VGA extension ROM
+#option ROM_SIZE = (512*1024)-(36*1024)
+option ROM_SIZE = (512*1024)
+
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+option FALLBACK_SIZE = 256*1024
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+option ROM_IMAGE_SIZE = 128*1024
+
+
+## We do use compressed image ?
+#option CONFIG_COMPRESS = 0
+
+###
+### Console Options
+###
+option CONFIG_CONSOLE_SERIAL8250 = 1
+option TTYS0_BAUD = 115200
+option CONFIG_CONSOLE_BTEXT = 1
+
+###
+### Build Code for VGA support
+###
+#option CONFIG_CONSOLE_VGA = 0
+#option CONFIG_PCI_ROM_RUN = 0
+#option CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST = 0
+
###
### Build code for SMP support
### Only worry about 2 micro processors
###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-#option CONFIG_LOGICAL_CPUS=2
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
+# option CONFIG_SMP = 1
+# option CONFIG_MAX_CPUS = 2
+# option CONFIG_MAX_PHYSICAL_CPUS = 2
+# option CONFIG_LOGICAL_CPUS = 0
+
+
###
### Build code to setup a generic IOAPIC
###
-option CONFIG_IOAPIC=1
-#
+# option CONFIG_IOAPIC = 1
+
+
###
### MEMORY_HOLE instructs earlymtrr.inc to
### enable caching from 0-640KB and to disable
@@ -47,40 +84,13 @@
### CPU identification depends on only variable MTRRs
### being enabled.
###
-#option MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option MAINBOARD_PART_NUMBER="DK8HTX"
-option MAINBOARD_VENDOR="Iwill"
-#
-###
-### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
-###
-#option FALLBACK_SIZE=524288
-#option FALLBACK_SIZE=98304
-option FALLBACK_SIZE=256*1024
+# option MEMORY_HOLE = 0
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-option ROM_IMAGE_SIZE=128*1024
-
###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
+### Logging/Debug Options
###
-
-## We do use compressed image
-#option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option TTYS0_BAUD=115200
-
-##
-### Select the linuxBIOS loglevel
+## Select the linuxBIOS loglevel:
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
@@ -93,58 +103,65 @@
## SPEW 9 Way too many details
## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=7
+option DEFAULT_CONSOLE_LOGLEVEL = 9
## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=7
-
-#option DEBUG=1
-
-#
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x004000
##
## Use a 32K stack
##
-option STACK_SIZE=0x8000
+#option STACK_SIZE = 0x8000
+
##
## Use a 56K heap
##
-option HEAP_SIZE=0xe000
+#option HEAP_SIZE = 0xe000
+
-#
###
### Compute the start location and size size of
### The linuxBIOS bootloader.
###
-option CONFIG_ROM_STREAM = 1
+## LinuxBIOS C code runs at this location in RAM
+#option _RAMBASE = 0x00004000
-#
-#
+#option CONFIG_ROM_STREAM = 1
+
+###
+### HT Config Options
+###
+## this will make SB hypertransport chain sit on bus 0,
+## if it is 2 will put other chain on 0x40, 0x80, 0xc0
+option K8_SB_HT_CHAIN_ON_BUS0 = 1
+
+###
+### special Performance options for AMD K8 Processors (SMP)
+###
+#2G memory hole
+#option K8_HW_MEM_HOLE_SIZEK=0x200000
+#option K8_HW_MEM_HOLE_SIZE_AUTO_INC=1
+
+###
+### Images
+###
romimage "normal"
-# 48K for SCSI FW
-# option ROM_SIZE = 512*1024-48*1024
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 512*1024-48*1024-48*1024
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
- option USE_FALLBACK_IMAGE=0
- option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- option ROM_SECTION_OFFSET= 0
+ option LINUXBIOS_EXTRA_VERSION = "$(shell cat ../../VERSION)_Normal"
+ option USE_FALLBACK_IMAGE = 0
+ option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
+ option ROM_SECTION_OFFSET = 0
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+ option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
+ option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
+ option XIP_ROM_SIZE = 65536
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-# payload /usr/src/filo-0.4.1_btext/filo.elf
- payload /tmp/filo.elf
-# payload /usr/src/filo-0.4.2/filo.elf
+# payload /home/pdegler/payloads/grub_e1000--filo.zelf
+ payload /home/pdegler/payloads/filo.elf
end
romimage "fallback"
@@ -153,16 +170,15 @@
option ROM_SECTION_SIZE = FALLBACK_SIZE
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+ option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
+ option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-# option XIP_ROM_SIZE = FALLBACK_SIZE
option XIP_ROM_SIZE = 65536
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
- payload /tmp/filo.elf
-# payload /usr/src/filo-0.4.2/filo.elf
+# payload /home/pdegler/payloads/e1000--filo.zelf
+ payload /home/pdegler/payloads/filo.elf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
--
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