Peter Stuge schrieb: >> the manual states two separate memories: expansion rom and then the >> rest of the flash mem. >> I am somewhat sure it is not purely a PCI expansion ROM . >> > > No it is definately not just an expansion ROM, but my point was that > they designed it to hook into the system boot process with an > expansion ROM that knew how to reach the rest of the flash. > > More generally speaking the board is overkill for our purposes since > we only need a much simpler FPGA and less flash memory, since no > chipset currently decodes more than 1MB at 4G anyway. Also their > design uses lots of flash chips which is not really neccessary today > when much larger flash chips are available. > > > >> maybe one should look at the verilog code stuff. >> > > So I did, the top 7 bits (31-25) of the board's BAR0 set which > address it listens to (PCI config space 0x10) and bits 22-2 are taken > from the PCI read cycle. > > Bits 24-23 are ignored, so there are 2^23 effective addresses, each > accessing a 32-bit word, total 32Mb. > > As for access to the expansion ROM, the VHDL is not complete. > Specifically the signal ROM_HIT isn't set anywhere. It's likely to > be set in the generic Xilinx LogiCORE VHDL for PCI devices. > > > >> Intel does not sell the board but one might find the manual >> interesting since it deals with our issue on a sidenote I believe. >> > > Sure, "all" that is needed to make such a PCI card is an FPGA and > flash memory. :) > > > //Pete sry this got misaddressed
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