Here's a first patch for the IGEL Winnet III thin client. It allows me to boot a Linux kernel half-way to the login prompt; at some point it hangs, though, so more work is needed.
This is a 233 MHz Geode GX1 based thin client with Ethernet, USB, VGA, a Disk-on-Chip, socketed DIP BIOS chip, a laptop-size RAM slot, a normal-size (PC) RAM slot (don't remember the correct name right now), and IDE connector, keyboard, mouse, sound, 2x serial port, parallel port, 1x ISA slot, 1x PCI slot. Fanless, extremely silent. Ca. 20-30 Euro via eBay. More details later, I'll write up a HOWTO for the wiki... Attached is a boot log, and some lspci and other useful output gathered from a Linux system booted using the original BIOS. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Add initial support for the ASI/BCom MB-5BLMP mainboard, as used in
the IGEL Winnet III thin client.
It boots a Linux kernel, but there are some problems. The login
prompt is never reached, it simply hangs at some point.
One possible reason is the IRQ table, which needs fixing.
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Index: src/mainboard/asi/mb_5blmp/Config.lb
===================================================================
--- src/mainboard/asi/mb_5blmp/Config.lb (Revision 0)
+++ src/mainboard/asi/mb_5blmp/Config.lb (Revision 0)
@@ -0,0 +1,209 @@
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+if HAVE_PIRQ_TABLE
+ object irq_tables.o
+end
+
+##
+## Romcc output
+##
+# makerule ./failover.E
+# depends "$(MAINBOARD)/failover.c ./romcc"
+# action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+# end
+#
+# makerule ./failover.inc
+# depends "$(MAINBOARD)/failover.c ./romcc"
+# action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+# end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c ./romcc"
+ action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c ./romcc"
+ action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+# if USE_FALLBACK_IMAGE
+# ldscript /arch/i386/lib/failover.lds
+# mainboardinit ./failover.inc
+# end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/amd/model_gx1/cpu_setup.inc
+mainboardinit cpu/amd/model_gx1/gx_setup.inc
+mainboardinit ./auto.inc
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+chip northbridge/amd/gx1 # Northbridge
+ device pci_domain 0 on
+ device pci 0.0 on end
+ chip southbridge/amd/cs5530 # Southbridge
+ device pci 12.0 on
+ chip superio/nsc/pc87351 # Super I/O
+ device pnp 2e.0 on # PIC
+ io 0x60 = 0x20
+ io 0x62 = 0xa0
+ irq 0x70 = 2
+ end
+ device pnp 2e.1 on # DMA
+ end
+ device pnp 2e.2 on # System Timer
+ io 0x60 = 0x40
+ irq 0x70 = 0
+ end
+ device pnp 2e.3 on # RTC
+ io 0x60 = 0x70
+ irq 0x70 = 8
+ end
+ device pnp 2e.4 on # Keyboard + Mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.5 on # PC Speaker
+ end
+ device pnp 2e.6 on # Math Coprocessor (FPU)
+ io 0x60 = 0xf0
+ irq 0x70 = 13
+ end
+ device pnp 2e.7 on # System board
+ end
+ device pnp 2e.8 on # Motherboard resources
+ end
+ device pnp 2e.9 on # PCI bus
+ end
+ device pnp 2e.c on # Motherboard resources
+ end
+ device pnp 2e.d on # Motherboard resources
+ end
+ device pnp 2e.e on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.f off # FDC
+ end
+ device pnp 2e.10 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.12 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ end
+ device pci 12.1 off end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 off end # Audio
+ device pci 12.4 off end # Video (VGA)
+ end
+ # device pci 12.4 on # VGA (onboard)
+ # chip drivers/pci/onboard
+ # device pci 12.4 on end
+ # register "rom_address" = "0xfffc0000" # 256 KB image
+ # # register "rom_address" = "0xfff80000" # 512 KB image
+ # # register "rom_address" = "0xfff00000" # 1 MB image
+ # end
+ # end
+ device pci 0f.0 off end # Ethernet (Realtek RTL8139B)
+ device pci 13.0 on end # USB
+ end
+ end
+
+ chip cpu/amd/model_gx1 # CPU
+ end
+
+end
+
Index: src/mainboard/asi/mb_5blmp/irq_tables.c
===================================================================
--- src/mainboard/asi/mb_5blmp/irq_tables.c (Revision 0)
+++ src/mainboard/asi/mb_5blmp/irq_tables.c (Revision 0)
@@ -0,0 +1,39 @@
+/* TODO: This is currently copied from the IEI NOVA-4899R target, but it's
+ * quite surely wrong for this board. It gets me further in the boot process
+ * than using no irq_tables.c file at all, though!
+ */
+
+/* TODO: Add license header. */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*5, /* there can be total 5 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0xe00, /* IRQs devoted exclusively to PCI usage */
+ 0x1078, /* Vendor */
+ 0x0002, /* Device */
+ 0, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x2d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ // USB
+ {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
+ // eth0
+ {0x00,(0x0a<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x3, 0x0},
+ // eth1
+ {0x00,(0x0b<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x2, 0x0},
+ // eth2
+ {0x00,(0x0c<<3)|0x0, {{0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x1, 0x0},
+ // PCI slot
+ {0x00,(0x0f<<3)|0x0, {{0x04, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
+ }
+};
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
Index: src/mainboard/asi/mb_5blmp/Options.lb
===================================================================
--- src/mainboard/asi/mb_5blmp/Options.lb (Revision 0)
+++ src/mainboard/asi/mb_5blmp/Options.lb (Revision 0)
@@ -0,0 +1,160 @@
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses CONFIG_ROM_PAYLOAD
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD_START
+# uses CONFIG_COMPRESS
+# uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+# uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+# uses CONFIG_CONSOLE_VGA
+# uses CONFIG_PCI_ROM_RUN
+
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE = 256 * 1024
+
+###
+### Build options
+###
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=0
+
+## Delay timer options
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=5 # TODO?
+
+##
+## Build code to export a CMOS option table
+##
+# default HAVE_OPTION_TABLE=0
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 64 * 1024
+default FALLBACK_SIZE = 128 * 1024
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+# default USE_OPTION_TABLE = 0
+
+default _RAMBASE = 0x00004000
+
+default CONFIG_ROM_PAYLOAD = 1
+
+##
+## The default compiler
+##
+default CROSS_COMPILE=""
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default DEFAULT_CONSOLE_LOGLEVEL=9
+## At a maximum only compile in this level of debugging
+default MAXIMUM_CONSOLE_LOGLEVEL=9
+
+# VGA Console
+# default CONFIG_CONSOLE_VGA=1
+# default CONFIG_PCI_ROM_RUN=1
+
+end
+
Index: src/mainboard/asi/mb_5blmp/auto.c
===================================================================
--- src/mainboard/asi/mb_5blmp/auto.c (Revision 0)
+++ src/mainboard/asi/mb_5blmp/auto.c (Revision 0)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "northbridge/amd/gx1/raminit.c"
+#include "superio/nsc/pc87351/pc87351_early_serial.c"
+#include "cpu/x86/bist.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
+
+static void main(unsigned long bist)
+{
+ /* Initialize the serial console. */
+ pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure. */
+ report_bist_failure(bist);
+
+ /* Initialize RAM. */
+ sdram_init();
+
+ /* Check whether RAM works. */
+ /* ram_check(0x00000000, 0x4000); */
+}
Index: src/mainboard/asi/mb_5blmp/chip.h
===================================================================
--- src/mainboard/asi/mb_5blmp/chip.h (Revision 0)
+++ src/mainboard/asi/mb_5blmp/chip.h (Revision 0)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_asi_mb_5blmp_ops;
+
+struct mainboard_asi_mb_5blmp_config {
+ int nothing;
+};
Index: src/mainboard/asi/mb_5blmp/mainboard.c
===================================================================
--- src/mainboard/asi/mb_5blmp/mainboard.c (Revision 0)
+++ src/mainboard/asi/mb_5blmp/mainboard.c (Revision 0)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_asi_mb_5blmp_ops = {
+ CHIP_NAME("ASI/BCom MB-5BLMP Mainboard")
+};
+
Index: targets/asi/mb_5blmp/Config.lb
===================================================================
--- targets/asi/mb_5blmp/Config.lb (Revision 0)
+++ targets/asi/mb_5blmp/Config.lb (Revision 0)
@@ -0,0 +1,43 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+target mb_5blmp
+mainboard asi/mb_5blmp
+
+option ROM_SIZE = (256 * 1024)
+# option ROM_SIZE = (256 * 1024) - (32 * 1024)
+# option FALLBACK_SIZE = (256 * 1024) - (32 * 1024)
+
+romimage "normal"
+ option USE_FALLBACK_IMAGE = 0
+ option ROM_IMAGE_SIZE = 64 * 1024
+ option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+ payload /tmp/filo.elf
+end
+
+romimage "fallback"
+ option USE_FALLBACK_IMAGE = 1
+ option ROM_IMAGE_SIZE = 64 * 1024
+ option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+ payload /tmp/filo.elf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+# buildrom ./linuxbios.rom ROM_SIZE "fallback"
$ lspci
00:00.0 Host bridge: Cyrix Corporation PCI Master
00:0f.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ (rev 10)
00:12.0 ISA bridge: Cyrix Corporation 5530 Legacy [Kahlua]
00:12.1 Bridge: Cyrix Corporation 5530 SMI [Kahlua]
00:12.2 IDE interface: Cyrix Corporation 5530 IDE [Kahlua]
00:12.3 Multimedia audio controller: Cyrix Corporation 5530 Audio [Kahlua]
00:12.4 VGA compatible controller: Cyrix Corporation 5530 Video [Kahlua]
00:13.0 USB Controller: Compaq Computer Corporation ZFMicro Chipset USB (rev 06)
$ lspci -nn
00:00.0 Host bridge [0600]: Cyrix Corporation PCI Master [1078:0001]
00:0f.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ [10ec:8139] (rev 10)
00:12.0 ISA bridge [0601]: Cyrix Corporation 5530 Legacy [Kahlua] [1078:0100]
00:12.1 Bridge [0680]: Cyrix Corporation 5530 SMI [Kahlua] [1078:0101]
00:12.2 IDE interface [0101]: Cyrix Corporation 5530 IDE [Kahlua] [1078:0102]
00:12.3 Multimedia audio controller [0401]: Cyrix Corporation 5530 Audio
[Kahlua] [1078:0103]
00:12.4 VGA compatible controller [0300]: Cyrix Corporation 5530 Video [Kahlua]
[1078:0104]
00:13.0 USB Controller [0c03]: Compaq Computer Corporation ZFMicro Chipset USB
[0e11:a0f8] (rev 06)
$ lspci -tv
-[0000:00]-+-00.0 Cyrix Corporation PCI Master
+-0f.0 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+
+-12.0 Cyrix Corporation 5530 Legacy [Kahlua]
+-12.1 Cyrix Corporation 5530 SMI [Kahlua]
+-12.2 Cyrix Corporation 5530 IDE [Kahlua]
+-12.3 Cyrix Corporation 5530 Audio [Kahlua]
+-12.4 Cyrix Corporation 5530 Video [Kahlua]
\-13.0 Compaq Computer Corporation ZFMicro Chipset USB
$ cat /proc/cpuinfo
processor : 0
vendor_id : CyrixInstead
cpu family : 5
model : 7
model name : Cyrix MediaGXtm MMXtm Enhanced
stepping : 4
cpu MHz : 233.884
cache size : 16 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 2
wp : yes
flags : fpu tsc msr cx8 cmov mmx cxmmx up
bogomips : 476.30
$ lspci -s 0:0.0 -xxx
00:00.0 Host bridge: Cyrix Corporation PCI Master
00: 78 10 01 00 07 00 80 02 00 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 1e 14 00 c1 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
$ lspnp
00:00 PNP0000 AT programmable interrupt controller
00:01 PNP0200 AT DMA controller
00:02 PNP0100 AT system timer
00:03 PNP0b00 AT real-time clock
00:04 PNP0303 IBM enhanced keyboard (101/102-key, PS/2 mouse support)
00:05 PNP0800 AT speaker
00:06 PNP0c04 Math coprocessor
00:07 PNP0c01 System board
00:08 PNP0c02 Motherboard resources
00:09 PNP0a03 PCI bus
00:0c PNP0c02 Motherboard resources
00:0d PNP0c02 Motherboard resources
00:0e PNP0501 16550A-compatible serial port
00:0f PNP0700 PC standard floppy disk controller
00:10 PNP0400 Standard LPT printer port
00:12 PNP0501 16550A-compatible serial port
$ lspnp -v
00:00 PNP0000 AT programmable interrupt controller
state = active
io 0x20-0x21
io 0xa0-0xa1
irq 2
00:01 PNP0200 AT DMA controller
state = active
io 0x0-0xf
io 0x81-0x83
io 0x87-0x87
io 0x89-0x8b
io 0x8f-0x91
io 0xc0-0xdf
dma 4
00:02 PNP0100 AT system timer
state = active
io 0x40-0x43
irq 0
00:03 PNP0b00 AT real-time clock
state = active
io 0x70-0x71
irq 8
00:04 PNP0303 IBM enhanced keyboard (101/102-key, PS/2 mouse support)
state = active
io 0x60-0x60
io 0x64-0x64
irq 1
00:05 PNP0800 AT speaker
state = active
io 0x61-0x61
00:06 PNP0c04 Math coprocessor
state = active
io 0xf0-0xff
irq 13
00:07 PNP0c01 System board
state = active
mem 0x0-0x9ffff
mem 0x40010000-0x40010fff
mem 0x40008000-0x4000ffff
mem 0x40018000-0x407fffff
00:08 PNP0c02 Motherboard resources
state = active
mem 0xf0000-0xf3fff
mem 0xf4000-0xf7fff
mem 0xf8000-0xfffff
mem 0xc8000-0xc9fff
00:09 PNP0a03 PCI bus
state = active
io 0x4d0-0x4d1
io 0xcf8-0xcff
io 0x480-0x48f
00:0c PNP0c02 Motherboard resources
state = active
mem 0xe0000-0xeffff
00:0d PNP0c02 Motherboard resources
state = active
io 0x800-0x80f
io 0x900-0x90f
00:0e PNP0501 16550A-compatible serial port
state = active
io 0x3f8-0x3ff
irq 4
00:0f PNP0700 PC standard floppy disk controller
state = active
io 0x3f2-0x3f5
irq 6
dma 2
00:10 PNP0400 Standard LPT printer port
state = active
io 0x378-0x37f
irq 7
00:12 PNP0501 16550A-compatible serial port
state = active
io 0x2f8-0x2ff
irq 3
/proc/devices:
Character devices:
1 mem
2 pty
3 ttyp
4 /dev/vc/0
4 tty
4 ttyS
5 /dev/tty
5 /dev/console
5 /dev/ptmx
7 vcs
10 misc
13 input
14 sound
29 fb
128 ptm
136 pts
180 usb
189 usb_device
Block devices:
1 ramdisk
2 fd
3 ide0
7 loop
254 device-mapper
---
/proc/interrupts:
CPU0
0: 125858 XT-PIC timer
1: 8 XT-PIC i8042
2: 0 XT-PIC cascade
7: 0 XT-PIC parport0
8: 4 XT-PIC rtc
11: 1206 XT-PIC eth0
14: 3525 XT-PIC ide0
15: 0 XT-PIC ohci_hcd:usb1
NMI: 0
LOC: 0
ERR: 0
MIS: 0
---
/proc/iomem:
00000000-0009efff : System RAM
00000000-00000000 : Crash kernel
000a0000-000bffff : Video RAM area
000c0000-000c7fff : Video ROM
000d8000-000d9fff : Adapter ROM
000da000-000dbfff : Adapter ROM
000f0000-000fffff : System ROM
00100000-05bfffff : System RAM
00100000-002728b6 : Kernel code
002728b7-002fab6f : Kernel data
40011000-4001107f : 0000:00:12.3
40012000-400120ff : 0000:00:12.1
40800000-40ffffff : 0000:00:12.4
d8000000-d80000ff : 0000:00:0f.0
d8000000-d80000ff : 8139too
d8004000-d8004fff : 0000:00:13.0
d8004000-d8004fff : ohci_hcd
---
/proc/ioports
0000-001f : dma1
0020-0021 : pic1
0040-0043 : timer0
0050-0053 : timer1
0060-006f : keyboard
0070-0077 : rtc
0080-008f : dma page reg
00a0-00a1 : pic2
00c0-00df : dma2
00f0-00ff : fpu
01f0-01f7 : ide0
02f8-02ff : serial
0378-037a : parport0
037b-037f : parport0
03c0-03df : vga+
03f6-03f6 : ide0
03f8-03ff : serial
0800-080f : pnp 00:0d
0900-090f : pnp 00:0d
e000-e0ff : 0000:00:0f.0
e000-e0ff : 8139too
f000-f00f : 0000:00:12.2
f000-f007 : ide0
f008-f00f : ide1
---
$ lsmod
Module Size Used by
ipv6 222304 12
loop 14888 0
evdev 9088 0
psmouse 34600 0
kahlua 4384 0
sb_lib 41060 1 kahlua
uart401 11140 1 sb_lib
sound 69672 2 sb_lib,uart401
soundcore 9216 2 sb_lib,sound
serio_raw 6596 0
parport_pc 32132 0
pcspkr 3040 0
parport 33160 1 parport_pc
8250_pnp 8704 0
rtc 12340 0
floppy 54276 0
ext3 118568 6
jbd 50292 1 ext3
mbcache 8324 1 ext3
dm_mirror 18768 0
dm_snapshot 15680 0
dm_mod 49944 9 dm_mirror,dm_snapshot
ide_generic 1376 0 [permanent]
ide_disk 15072 3
generic 4420 0 [permanent]
cs5530 5152 0 [permanent]
8139too 24800 0
ide_core 111016 4 ide_generic,ide_disk,generic,cs5530
8139cp 20576 0
mii 5312 2 8139too,8139cp
ohci_hcd 18244 0
usbcore 111616 2 ohci_hcd
processor 25512 0
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