Hi Jeremy, On Saturday 02 June 2007 20:25, Jeremy Jackson wrote: > Can you please explain which chipset northbridge does this? I've never > seen one that uses the PCI bus in this fashion, but I'd like to know if > there is one.
Sorry, I had no special x86 chipset in mind. This is only a possible scenario one can use to save an additional bus mostly used at system start up only. I only know a PowerPC (405GP if I remember right, its a SoC) processor that supports such kind of ROM device addressing/connecting. > http://www.intel.com/design/chipsets/440/documentation.htm > > Everyone, please look at Intel 440BX chipset docs for a clear > explanation. It's an older chipset but that helps to explain the > history of some things. > > Northbridge 440BX > > http://www.intel.com/design/chipsets/datashts/290633.htm > > Page 1-2 has an excellent system diagram. And it shows the ROM is connected to the ISA bus, behind the southbridge. Nothing PCI specific. > Southbridge PIIX4E: > > http://www.intel.com/design/intarch/datashts/290562.htm > > Page 12 has another useful system diagram showing the BIOS. > > The PIIX4E i82371EB claims the 0xFFFF_FFF0 cycle, and aliases to top of > X-bus (1M and 16M) which is where the BIOS rom is connected. This is > done after reset, even without PCI configuration, as a special case to > allow booting. > > Page 155 gives the details. Seems also the ISA bus is where the ROM device is connected to. And to reach the ISA bus, you must reach the southbridge first. So that's why the PCI bus is relevant here. But not to access the ROM device itself. So it does not match my scenario where the ROM device is directly connected to PCI lines. Juergen -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
