See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Improve support for the Intel 82371AB/EB/MB southbridge:
- Implement ISA related support:
- Initialize the RTC
- Enable access to all BIOS regions (but _not_ write access to ROM)
- Enable ISA (not EIO) support
- Improve IDE support:
- Add config option to enable Ultra DMA/33 for each disk
- Add config option to enable legacy IDE port access
- Implement hard reset support
- Implement USB controller support
- Various code cleanups and improvements
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Index: src/southbridge/intel/i82371eb/Config.lb
===================================================================
--- src/southbridge/intel/i82371eb/Config.lb (Revision 2718)
+++ src/southbridge/intel/i82371eb/Config.lb (Arbeitskopie)
@@ -21,6 +21,9 @@
config chip.h
driver i82371eb.o
+driver i82371eb_isa.o
+driver i82371eb_ide.o
+driver i82371eb_uhci.o
driver i82371eb_smbus.o
-driver i82371eb_ide.o
+driver i82371eb_reset.o
Index: src/southbridge/intel/i82371eb/i82371eb_isa.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_isa.c (Revision 0)
+++ src/southbridge/intel/i82371eb/i82371eb_isa.c (Revision 0)
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+static void isa_init(struct device *dev)
+{
+ uint16_t reg16;
+ uint32_t reg32;
+
+ /* TODO: Make all of this stuff configurable. */
+
+ /* TODO: I/O APIC? */
+
+ /* TODO: Enable serial IRQs? */
+
+ /* Initialize the real time clock (RTC). */
+ rtc_init(0);
+
+ /**
+ * Enable access to all BIOS regions. Do not enable write access to
+ * the ROM.
+ */
+ reg16 = pci_read_config16(dev, XBCS);
+ reg16 |= LOWER_BIOS_ENABLE;
+ reg16 |= EXTENDED_BIOS_ENABLE;
+ reg16 |= ONE_MEG_EXTENDED_BIOS_ENABLE;
+ reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */
+ pci_write_config16(dev, XBCS, reg16);
+
+ /* The PIIX4 can support the full Industry Standard Architecture (ISA)
+ * bus, or the Extended I/O (EIO) bus, which is a subset of ISA.
+ * We select the full ISA bus here.
+ */
+ reg32 = pci_read_config32(dev, GENCFG);
+ reg32 |= ISA; /* Select ISA, not EIO. */
+ pci_write_config16(dev, GENCFG, reg32);
+
+ /* TODO: Initialize ISA DMA? */
+
+ /* TODO: Initialize the High Precision Event Timers (HPET) if any? */
+
+ /* TODO: Enable access to the upper 128 byte bank of CMOS RAM? */
+}
+
+static struct device_operations isa_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = isa_init,
+ .scan_bus = scan_static_bus, /* TODO: Needed? */
+ .enable = 0,
+ .ops_pci = 0, /* No subsystem IDs on 82371EB! */
+};
+
+static struct pci_driver isa_driver __pci_driver = {
+ .ops = &isa_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_82371AB_ISA,
+};
Index: src/southbridge/intel/i82371eb/i82371eb.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb.c (Revision 2718)
+++ src/southbridge/intel/i82371eb/i82371eb.c (Arbeitskopie)
@@ -25,39 +25,15 @@
* - Order Number: 290562-001
*/
-#include <console/console.h>
#include <device/device.h>
-#include <device/pci.h>
#include "i82371eb.h"
-/**
- * Enable access to all BIOS regions. Do not enable write access to the ROM.
- *
- * XBCS register bits:
- * - Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
- * FFF00000-FFF7FFFF are forwarded to ISA).
- * - Set bit 7: Extended BIOS Enable (PCI master accesses to
- * FFF80000-FFFDFFFF are forwarded to ISA).
- * - Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
- * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
- * of 1 Mbyte, or the aliases at the top of 4 Gbyte
- * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
- * - Bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
- *
- * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
- *
- * @param dev The device to use.
- */
void i82371eb_enable(device_t dev)
{
- uint16_t reg;
-
- reg = pci_read_config16(dev, XBCS);
- reg |= 0x2c0;
- pci_write_config16(dev, XBCS, reg);
+ /* TODO: Nothing to do? */
}
struct chip_operations southbridge_intel_i82371eb_ops = {
- CHIP_NAME("Intel 82371EB Southbridge")
+ CHIP_NAME("Intel 82371AB/EB/MB Southbridge")
.enable_dev = i82371eb_enable,
};
Index: src/southbridge/intel/i82371eb/i82371eb_ide.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_ide.c (Revision 2718)
+++ src/southbridge/intel/i82371eb/i82371eb_ide.c (Arbeitskopie)
@@ -28,36 +28,115 @@
* Initialize the IDE controller.
*
* Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
- * we enable or disable the primary and secondary IDE interface, respectively.
+ * enable or disable the primary and secondary IDE interface, respectively.
*
+ * Depending on the configuration variables 'ide0_drive0_udma33_enable',
+ * 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and
+ * 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for
+ * the respective drive.
+ *
+ * Depending on the configuration variable 'ide_legacy_enable' enable or
+ * disable access to the legacy IDE ports and the PCI Bus Master IDE I/O
+ * registers.
+ *
* @param dev The device to use.
*/
static void ide_init(struct device *dev)
{
- uint16_t reg;
+ uint8_t reg8;
+ uint16_t reg16;
struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
/* Enable/disable the primary IDE interface. */
- reg = pci_read_config16(dev, IDETIM_PRI);
+ reg16 = pci_read_config16(dev, IDETIM_PRI);
if (conf->ide0_enable) {
- reg |= IDE_DECODE_ENABLE;
+ reg16 |= IDE_DECODE_ENABLE;
print_info("Primary IDE interface enabled\n");
} else {
- reg &= ~(IDE_DECODE_ENABLE);
+ reg16 &= ~(IDE_DECODE_ENABLE);
print_info("Primary IDE interface disabled\n");
}
- pci_write_config16(dev, IDETIM_PRI, reg);
+ pci_write_config16(dev, IDETIM_PRI, reg16);
+ if (conf->ide0_enable) {
+ /* Enable/disable UDMA/33 operation (primary IDE interface). */
+ reg8 = pci_read_config8(dev, UDMACTL);
+ if (conf->ide0_drive0_udma33_enable) {
+ reg8 |= PSDE0;
+ print_info("Primary IDE, drive 0: UDMA/33 on\n");
+ } else {
+ reg8 &= ~(PSDE0);
+ print_info("Primary IDE, drive 0: UDMA/33 off\n");
+ }
+ if (conf->ide0_drive1_udma33_enable) {
+ reg8 |= PSDE1;
+ print_info("Primary IDE, drive 1: UDMA/33 on\n");
+ } else {
+ reg8 &= ~(PSDE1);
+ print_info("Primary IDE, drive 1: UDMA/33 off\n");
+ }
+ pci_write_config8(dev, UDMACTL, reg8);
+
+ /* TODO */
+ reg8 = pci_read_config8(dev, IDETIM_PRI);
+ reg8 |= DTE0;
+ reg8 |= DTE1;
+ pci_write_config8(dev, IDETIM_PRI, reg8);
+ }
+
/* Enable/disable the secondary IDE interface. */
- reg = pci_read_config16(dev, IDETIM_SEC);
+ reg16 = pci_read_config16(dev, IDETIM_SEC);
if (conf->ide1_enable) {
- reg |= IDE_DECODE_ENABLE;
+ reg16 |= IDE_DECODE_ENABLE;
print_info("Secondary IDE interface enabled\n");
} else {
- reg &= ~(IDE_DECODE_ENABLE);
+ reg16 &= ~(IDE_DECODE_ENABLE);
print_info("Secondary IDE interface disabled\n");
}
- pci_write_config16(dev, IDETIM_SEC, reg);
+ pci_write_config16(dev, IDETIM_SEC, reg16);
+
+ /* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */
+ if (conf->ide1_enable) {
+ reg8 = pci_read_config8(dev, UDMACTL);
+ if (conf->ide1_drive0_udma33_enable) {
+ reg8 |= SSDE0;
+ print_info("Secondary IDE, drive 0: UDMA/33 on\n");
+ } else {
+ reg8 &= ~(SSDE0);
+ print_info("Secondary IDE, drive 0: UDMA/33 off\n");
+ }
+ if (conf->ide1_drive1_udma33_enable) {
+ reg8 |= SSDE1;
+ print_info("Secondary IDE, drive 1: UDMA/33 on\n");
+ } else {
+ reg8 &= ~(SSDE1);
+ print_info("Secondary IDE, drive 1: UDMA/33 off\n");
+ }
+ pci_write_config8(dev, UDMACTL, reg8);
+
+ /* TODO */
+ reg8 = pci_read_config8(dev, IDETIM_SEC);
+ reg8 |= DTE0;
+ reg8 |= DTE1;
+ pci_write_config8(dev, IDETIM_SEC, reg8);
+ }
+
+ /* Enable access to the legacy IDE ports (both primary and secondary),
+ * and the PCI Bus Master IDE I/O registers.
+ * Only do this if at least one IDE interface is enabled.
+ */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ if (conf->ide_legacy_enable &&
+ (conf->ide0_enable || conf->ide1_enable)) {
+ reg16 |= PCI_COMMAND_IO;
+ reg16 |= PCI_COMMAND_MASTER; // FIXME?
+ print_info("Access to legacy IDE ports enabled\n");
+ } else {
+ reg16 &= ~(PCI_COMMAND_IO);
+ reg16 &= ~(PCI_COMMAND_MASTER); // FIXME?
+ print_info("Access to legacy IDE ports disabled\n");
+ }
+ pci_write_config16(dev, PCI_COMMAND, reg16);
}
static struct device_operations ide_ops = {
@@ -66,6 +145,7 @@
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.scan_bus = 0,
+ .enable = 0,
.ops_pci = 0, /* No subsystem IDs on 82371EB! */
};
Index: src/southbridge/intel/i82371eb/i82371eb_reset.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_reset.c (Revision 0)
+++ src/southbridge/intel/i82371eb/i82371eb_reset.c (Revision 0)
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "i82371eb.h"
+
+/**
+ * Initiate a hard reset.
+ */
+void i82371eb_hard_reset(void)
+{
+ outb(SRST | RCPU, RC);
+}
Index: src/southbridge/intel/i82371eb/chip.h
===================================================================
--- src/southbridge/intel/i82371eb/chip.h (Revision 2718)
+++ src/southbridge/intel/i82371eb/chip.h (Arbeitskopie)
@@ -27,7 +27,12 @@
struct southbridge_intel_i82371eb_config {
int ide0_enable:1;
+ int ide0_drive0_udma33_enable:1;
+ int ide0_drive1_udma33_enable:1;
int ide1_enable:1;
+ int ide1_drive0_udma33_enable:1;
+ int ide1_drive1_udma33_enable:1;
+ int ide_legacy_enable:1;
int usb_enable:1;
};
Index: src/southbridge/intel/i82371eb/i82371eb.h
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb.h (Revision 2718)
+++ src/southbridge/intel/i82371eb/i82371eb.h (Arbeitskopie)
@@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef SOUTHBRIDGE_INTEL_I82371EB_H
-#define SOUTHBRIDGE_INTEL_I82371EB_H
+#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
+#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#ifndef __ROMCC__
#include "chip.h"
@@ -27,18 +27,39 @@
#endif
#define XBCS 0x4e /* X-Bus Chip Select register */
+#define GENCFG 0xb0 /* General configuration register */
+#define RC 0xcf9 /* Reset Control Register */
+/* IDE */
+#define IDETIM_PRI 0x40 /* IDE timing register, primary channel */
+#define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */
+#define UDMACTL 0x48 /* Ultra DMA/33 control register */
+#define UDMATIM 0x4a /* Ultra DMA/33 timing register */
+
/* SMBus */
#define SMBBA 0x90 /* SMBus Base Address */
#define SMBHSTCFG 0xd2 /* SMBus Host Configuration */
-/* IDE */
-#define IDETIM_PRI 0x40 /* IDE timing register, primary channel */
-#define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */
+/* Power management (ACPI) */
+#define PMBA 0x40 /* Power Management Base Address */
+#define PMREGMISC 0x80 /* Miscellaneous Power Management */
/* Bit definitions */
-#define IOSE (1 << 0) /* I/O Space Enable */
-#define SMB_HST_EN (1 << 0) /* Host Interface Enable */
-#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */
+#define ONE_MEG_EXTENDED_BIOS_ENABLE (1 << 9) /* 1-Meg Extended BIOS Enable */
+#define EXTENDED_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */
+#define LOWER_BIOS_ENABLE (1 << 6) /* Lower BIOS Enable */
+#define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */
+#define SRST (1 << 1) /* System Reset */
+#define RCPU (1 << 2) /* Reset CPU */
+#define SMB_HST_EN (1 << 0) /* Host Interface Enable */
+#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */
+#define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */
+#define DTE1 (1 << 7) /* DMA Timing Enable Only, drive 1 */
+#define PSDE0 (1 << 0) /* Primary Drive 0 UDMA/33 */
+#define PSDE1 (1 << 1) /* Primary Drive 1 UDMA/33 */
+#define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */
+#define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */
+#define ISA (1 << 0) /* Select ISA */
+#define EIO (0 << 0) /* Select EIO */
-#endif /* SOUTHBRIDGE_INTEL_I82371EB_H */
+#endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */
Index: src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_early_smbus.c (Revision 2718)
+++ src/southbridge/intel/i82371eb/i82371eb_early_smbus.c (Arbeitskopie)
@@ -50,7 +50,7 @@
/* Enable access to the SMBus I/O space. */
reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 |= IOSE;
+ reg16 |= PCI_COMMAND_IO;
pci_write_config16(dev, PCI_COMMAND, reg16);
/* Clear any lingering errors, so the transaction will run. */
Index: src/southbridge/intel/i82371eb/i82371eb_uhci.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_uhci.c (Revision 0)
+++ src/southbridge/intel/i82371eb/i82371eb_uhci.c (Revision 0)
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+/**
+ * Initialize the USB (UHCI) controller.
+ *
+ * Depending on the configuration variable 'usb_enable', enable or
+ * disable the USB (UHCI) controller.
+ *
+ * TODO: Is this even needed? Or are the usual PCI ops enough?
+ *
+ * @param dev The device to use.
+ */
+static void uhci_init(struct device *dev)
+{
+ uint16_t reg16;
+ struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
+
+ /* TODO: Set base? To which value? */
+
+ /* Enable/disable the USB (UHCI) controller. */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ if (conf->usb_enable) {
+ reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+ print_info("USB host controller enabled\n");
+ } else {
+ reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+ print_info("USB host controller disabled\n");
+ }
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+}
+
+static struct device_operations uhci_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = uhci_init,
+ .scan_bus = 0,
+ .enable = 0,
+ .ops_pci = 0, /* No subsystem IDs on 82371EB! */
+};
+
+static struct pci_driver uhci_driver __pci_driver = {
+ .ops = &uhci_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_82371AB_USB,
+};
Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_smbus.c (Revision 2718)
+++ src/southbridge/intel/i82371eb/i82371eb_smbus.c (Arbeitskopie)
@@ -24,6 +24,7 @@
#include <device/smbus.h>
#include "i82371eb.h"
+/* TODO: Needed later? */
static struct smbus_bus_operations lops_smbus_bus = {
};
@@ -33,7 +34,7 @@
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = scan_static_bus,
- // .enable = i82371eb_enable, // TODO: Needed?
+ .enable = 0,
.ops_pci = 0, /* No subsystem IDs on 82371EB! */
.ops_smbus_bus = &lops_smbus_bus,
};
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