Hello,
Corey or Uwe maybe you can help me with this. Does this look workable to you?
I'm just not sure with all this bit shifting it is going to return the
correct value. The DRC register has seperate bits for the commands and
the refreshes.
/* DRC[10:8] - Refresh Mode Select (RMS). */
#define RAM_COMMAND_REFRESH_1 0x1 /* Refresh interval 15.6 us for 133MHz */
#define RAM_COMMAND_REFRESH_2 0x2 /* Refresh interval 7.8 us for 133MHz */
#define RAM_COMMAND_REFRESH_3 0x7 /* Refresh interval 128 Clocks.
(Fast Refresh Mode) */
/* DRC[6:4] - SDRAM Mode Select (SMS). */
#define RAM_COMMAND_NOP 0x1
#define RAM_COMMAND_PRECHARGE 0x2
#define RAM_COMMAND_MRS 0x3
#define RAM_COMMAND_CBR 0x6
#define RAM_COMMAND_NORMAL 0x7
static void do_ram_command(const struct mem_controller *ctrl, uint32_t
command,
uint32_t addr_offset, uint32_t row_offset)
{
int i;
uint32_t reg;
/* TODO: Support for multiple DIMMs. */
/* Configure the RAM command. */
reg = pci_read_config32(ctrl->d0, DRC);
reg &= 0x0; /* Clear all bits to default: 00000000h. */
reg |= command << 4;
/* If RAM_COMMAND_NORMAL set the refresh mode and IC bit 29. */
if (command == RAM_COMMAND_NORMAL) {
reg |= ((RAM_COMMAND_REFRESH_1 << 8) | (1 << 29));
}
pci_write_config32(ctrl->d0, DRC, reg);
/* RAM_COMMAND_NORMAL affects only the memory controller and
doesn't need to be "sent" to the DIMMs. */
/* if (command == RAM_COMMAND_NORMAL) return; */
PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX32(reg);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME
PRINT_DEBUG("\r\n");
/* Read from (DIMM start address + addr_offset). */
read32(0 + addr_offset); //first offset is always 0
read32(row_offset + addr_offset);
}
Thanks - Joe
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