committed in 2728 Marc
Marc Jones wrote: > This patch for the dbe61 gets to loading the payload but then crashes. I > think that the SPD table may need more refinement. (Note that it is > working on a Norwich platform so there is a subtle difference I have not > found yet.) > > I felt like there was enough important stuff here to submit this patch. > I will continue to work with the Artec Group guys to get a working payload. > > Thanks, > Marc > > > ------------------------------------------------------------------------ > > ΓΏ > > LinuxBIOS-2.0.0.0Fallback Tue Jun 19 16:17:27 MDT 2007 starting... > _MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000598:00001822 > Configuring PLL > > > LinuxBIOS-2.0.0.0Fallback Tue Jun 19 16:17:27 MDT 2007 starting... > _MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000598:07de0022 > Done cpuRegInit > Ram1.00 > Ram2.00 > Ram3 > DRAM controller init done. > RAM DLL lock > Ram4 > Copying LinuxBIOS to ram. > Jumping to LinuxBIOS. > LinuxBIOS-2.0.0.0Fallback Tue Jun 19 16:17:27 MDT 2007 booting... > clocks_per_usec: 432 > Enumerating buses... > scan_static_bus for Root Device >>> Entering northbridge.c: enable_dev with path 6 >>> Entering northbridge.c: pci_domain_enable > Enter northbridge_init_early > writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 > writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 > writeglmsr: MSR 0x1000002c, val 0x20000000:0x00000003 > sizeram: _MSR MC_CF07_DATA: 10075012:00005740 > sizeram: sizem 0x80MB > SysmemInit: enable for 128MBytes > usable RAM: 134086655 bytes > SysmemInit: MSR 0x10000028, val 0x20000007:0xfdf00100 > sizeram: _MSR MC_CF07_DATA: 10075012:00005740 > sizeram: sizem 0x80MB > SMMGL0Init: 134086656 bytes > SMMGL0Init: offset is 0x80400000 > SMMGL0Init: MSR 0x10000026, val 0x287be080:0x400fffe0 > writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 > writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 > writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 > writeglmsr: MSR 0x4000002e, val 0x20000000:0x00000003 > sizeram: _MSR MC_CF07_DATA: 10075012:00005740 > sizeram: sizem 0x80MB > SysmemInit: enable for 128MBytes > usable RAM: 134086655 bytes > SysmemInit: MSR 0x4000002a, val 0x20000007:0xfdf00100 > SMMGL1Init: > SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0 > writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 > writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 > CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x107FDF00 > CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 > L2 cache enabled > Enabling cache > GLPCI R1: system msr.lo 0x00100130 msr.hi 0x07fdf000 > GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000 > Exit northbridge_init_early > Done cpubug fixes > Not Doing ChipsetFlashSetup() > Before VSA: > do_vsmbios > buf ilen 35441 olen60466 > buf 00060000 *buf 186 buf[256k] 247 > buf[0x20] signature is b0:10:e6:80 > Call real_mode_switch_call_vsm > biosint: INT# 0x15 > biosint: eax 0xbea7 ebx 0x4e53 ecx 0x10000026 edx 0x10000028 > biosint: ebp 0x15ed4 esp 0xff0 edi 0x8a71 esi 0x38 > biosint: ip 0x5b3 cs 0x6000 flags 0x46 > biosint: gs 0x0 fs 0x0 ds 0x6000 es 0x0 > handleint21, eax 0xbea7 > biosint: INT# 0x15 > biosint: eax 0xbea4 ebx 0x4e53 ecx 0x10000026 edx 0x10000028 > biosint: ebp 0x15ed4 esp 0xfee edi 0x8a71 esi 0x38 > biosint: ip 0x5c1 cs 0x6000 flags 0x46 > biosint: gs 0x0 fs 0x0 ds 0x6000 es 0x0 > handleint21, eax 0xbea4 > do_vsmbios: VSA2 VR signature verified > After VSA: > Graphics init... > VRC_VG value: 0x2808 > Finding PCI configuration type. > PCI: Using configuration type 1 > PCI_DOMAIN: 0000 enabled >>> Entering northbridge.c: enable_dev with path 7 > APIC_CLUSTER: 0 enabled > PCI_DOMAIN: 0000 scanning... >>> Entering northbridge.c: pci_domain_scan_bus > PCI: pci_scan_bus for bus 00 > PCI: devfn 0x0, bad id 0xffffffff >>> Entering northbridge.c: enable_dev with path 2 > PCI: 00:01.0 [1022/2080] ops > PCI: 00:01.0 [1022/2080] enabled >>> Entering northbridge.c: enable_dev with path 2 > PCI: 00:01.1 [1022/2081] enabled > malloc Enter, size 668, free_mem_ptr 00016000 > malloc 0x00016000 > PCI: 00:01.2 [1022/2082] enabled > PCI: devfn 0xb, bad id 0xffffffff > PCI: devfn 0xc, bad id 0xffffffff > PCI: devfn 0xd, bad id 0xffffffff > PCI: devfn 0xe, bad id 0xffffffff > PCI: devfn 0xf, bad id 0xffffffff > PCI: devfn 0x10, bad id 0xffffffff > PCI: devfn 0x18, bad id 0xffffffff > PCI: devfn 0x20, bad id 0xffffffff > PCI: devfn 0x28, bad id 0xffffffff > PCI: devfn 0x30, bad id 0xffffffff > PCI: devfn 0x38, bad id 0xffffffff > PCI: devfn 0x40, bad id 0xffffffff > PCI: devfn 0x48, bad id 0xffffffff > PCI: devfn 0x50, bad id 0xffffffff > cs5536: southbridge_enable: dev is 0000fce0 > Disabling static device: PCI: 00:0b.0 > PCI: devfn 0x59, bad id 0xffffffff > PCI: devfn 0x5a, bad id 0xffffffff > PCI: devfn 0x5b, bad id 0xffffffff > PCI: devfn 0x5c, bad id 0xffffffff > PCI: devfn 0x5d, bad id 0xffffffff > PCI: devfn 0x5e, bad id 0xffffffff > PCI: devfn 0x5f, bad id 0xffffffff > cs5536: southbridge_enable: dev is 0000ff80 > Disabling static device: PCI: 00:0c.0 > PCI: devfn 0x61, bad id 0xffffffff > PCI: devfn 0x62, bad id 0xffffffff > PCI: devfn 0x63, bad id 0xffffffff > PCI: devfn 0x64, bad id 0xffffffff > PCI: devfn 0x65, bad id 0xffffffff > PCI: devfn 0x66, bad id 0xffffffff > PCI: devfn 0x67, bad id 0xffffffff > cs5536: southbridge_enable: dev is 00010220 > PCI: 00:0d.0 [10ec/8139] enabled > cs5536: southbridge_enable: dev is 000104c0 > Disabling static device: PCI: 00:0e.0 > PCI: devfn 0x71, bad id 0xffffffff > PCI: devfn 0x72, bad id 0xffffffff > PCI: devfn 0x73, bad id 0xffffffff > PCI: devfn 0x74, bad id 0xffffffff > PCI: devfn 0x75, bad id 0xffffffff > PCI: devfn 0x76, bad id 0xffffffff > PCI: devfn 0x77, bad id 0xffffffff > cs5536: southbridge_enable: dev is 00010760 > PCI: 00:0f.0 [1022/2090] bus ops > PCI: 00:0f.0 [1022/2090] enabled > PCI: devfn 0x79, bad id 0xffffffff > cs5536: southbridge_enable: dev is 00010a00 > PCI: 00:0f.2 [1022/209a] ops > PCI: 00:0f.2 [1022/209a] enabled > cs5536: southbridge_enable: dev is 00010ca0 > PCI: 00:0f.3 [1022/2093] enabled > cs5536: southbridge_enable: dev is 00010f40 > PCI: 00:0f.4 [1022/2094] enabled > cs5536: southbridge_enable: dev is 000111e0 > PCI: 00:0f.5 [1022/2095] enabled > malloc Enter, size 668, free_mem_ptr 0001629c > malloc 0x0001629c > PCI: 00:0f.6 [1022/2096] enabled > malloc Enter, size 668, free_mem_ptr 00016538 > malloc 0x00016538 > PCI: 00:0f.7 [1022/2097] enabled > PCI: devfn 0x80, bad id 0xffffffff > PCI: devfn 0x88, bad id 0xffffffff > PCI: devfn 0x90, bad id 0xffffffff > PCI: devfn 0x98, bad id 0xffffffff > PCI: devfn 0xa0, bad id 0xffffffff > PCI: devfn 0xa8, bad id 0xffffffff > PCI: devfn 0xb0, bad id 0xffffffff > PCI: devfn 0xb8, bad id 0xffffffff > PCI: devfn 0xc0, bad id 0xffffffff > PCI: devfn 0xc8, bad id 0xffffffff > PCI: devfn 0xd0, bad id 0xffffffff > PCI: devfn 0xd8, bad id 0xffffffff > PCI: devfn 0xe0, bad id 0xffffffff > PCI: devfn 0xe8, bad id 0xffffffff > PCI: devfn 0xf0, bad id 0xffffffff > PCI: devfn 0xf8, bad id 0xffffffff > scan_static_bus for PCI: 00:0f.0 > scan_static_bus for PCI: 00:0f.0 done > PCI: pci_scan_bus returning with max=000 > scan_static_bus for Root Device done > done > Allocating resources... > Reading resources... > Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: > 0 > Root Device read_resources bus 0 link: 0 >>> Entering northbridge.c: pci_domain_read_resources > PCI_DOMAIN: 0000 read_resources bus 0 link: 0 > PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done > Root Device read_resources bus 0 link: 0 done > PCI: 00:0d.0 10 * [0x00000400 - 0x000004ff] io > PCI: 00:0f.0 14 * [0x00000800 - 0x000008ff] io > PCI: 00:0f.0 20 * [0x00000c00 - 0x00000c7f] io > PCI: 00:0f.3 10 * [0x00000c80 - 0x00000cff] io > PCI: 00:0f.0 18 * [0x00001000 - 0x0000103f] io > PCI: 00:0f.0 24 * [0x00001040 - 0x0000107f] io > PCI: 00:0f.0 1c * [0x00001080 - 0x0000109f] io > PCI: 00:0f.2 20 * [0x000010a0 - 0x000010af] io > PCI: 00:0f.0 10 * [0x000010b0 - 0x000010b7] io > PCI: 00:01.0 10 * [0x000010c0 - 0x000010c3] io > Root Device compute_allocate_io: base: 000010c4 size: 00000cc4 align: 8 gran: > 0 done > Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 > gran: 0 > Root Device read_resources bus 0 link: 0 > Root Device read_resources bus 0 link: 0 done > PCI: 00:01.1 10 * [0x00000000 - 0x00ffffff] mem > PCI: 00:01.1 14 * [0x01000000 - 0x01003fff] mem > PCI: 00:01.1 18 * [0x01004000 - 0x01007fff] mem > PCI: 00:01.1 1c * [0x01008000 - 0x0100bfff] mem > PCI: 00:01.1 20 * [0x0100c000 - 0x0100ffff] mem > PCI: 00:01.2 10 * [0x01010000 - 0x01013fff] mem > PCI: 00:0f.6 10 * [0x01014000 - 0x01015fff] mem > PCI: 00:0f.4 10 * [0x01016000 - 0x01016fff] mem > PCI: 00:0f.5 10 * [0x01017000 - 0x01017fff] mem > PCI: 00:0f.7 10 * [0x01018000 - 0x01018fff] mem > PCI: 00:0d.0 14 * [0x01019000 - 0x010190ff] mem > Root Device compute_allocate_mem: base: 01019100 size: 01019100 align: 24 > gran: 0 done > Done reading resources. > Setting resources... > Root Device compute_allocate_io: base: 00001000 size: 00000cc4 align: 8 gran: > 0 > Root Device read_resources bus 0 link: 0 > Root Device read_resources bus 0 link: 0 done > PCI: 00:0d.0 10 * [0x00001000 - 0x000010ff] io > PCI: 00:0f.0 14 * [0x00001400 - 0x000014ff] io > PCI: 00:0f.0 20 * [0x00001800 - 0x0000187f] io > PCI: 00:0f.3 10 * [0x00001880 - 0x000018ff] io > PCI: 00:0f.0 18 * [0x00001c00 - 0x00001c3f] io > PCI: 00:0f.0 24 * [0x00001c40 - 0x00001c7f] io > PCI: 00:0f.0 1c * [0x00001c80 - 0x00001c9f] io > PCI: 00:0f.2 20 * [0x00001ca0 - 0x00001caf] io > PCI: 00:0f.0 10 * [0x00001cb0 - 0x00001cb7] io > PCI: 00:01.0 10 * [0x00001cc0 - 0x00001cc3] io > Root Device compute_allocate_io: base: 00001cc4 size: 00000cc4 align: 8 gran: > 0 done > Root Device compute_allocate_mem: base: fd000000 size: 01019100 align: 24 > gran: 0 > Root Device read_resources bus 0 link: 0 > Root Device read_resources bus 0 link: 0 done > PCI: 00:01.1 10 * [0xfd000000 - 0xfdffffff] mem > PCI: 00:01.1 14 * [0xfe000000 - 0xfe003fff] mem > PCI: 00:01.1 18 * [0xfe004000 - 0xfe007fff] mem > PCI: 00:01.1 1c * [0xfe008000 - 0xfe00bfff] mem > PCI: 00:01.1 20 * [0xfe00c000 - 0xfe00ffff] mem > PCI: 00:01.2 10 * [0xfe010000 - 0xfe013fff] mem > PCI: 00:0f.6 10 * [0xfe014000 - 0xfe015fff] mem > PCI: 00:0f.4 10 * [0xfe016000 - 0xfe016fff] mem > PCI: 00:0f.5 10 * [0xfe017000 - 0xfe017fff] mem > PCI: 00:0f.7 10 * [0xfe018000 - 0xfe018fff] mem > PCI: 00:0d.0 14 * [0xfe019000 - 0xfe0190ff] mem > Root Device compute_allocate_mem: base: fe019100 size: 01019100 align: 24 > gran: 0 done > Root Device assign_resources, bus 0 link: 0 >>> Entering northbridge.c: pci_domain_set_resources > PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 > PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] mem > PCI: 00:01.1 14 <- [0x00fe000000 - 0x00fe003fff] mem > PCI: 00:01.1 18 <- [0x00fe004000 - 0x00fe007fff] mem > PCI: 00:01.1 1c <- [0x00fe008000 - 0x00fe00bfff] mem > PCI: 00:01.1 20 <- [0x00fe00c000 - 0x00fe00ffff] mem > PCI: 00:01.2 10 <- [0x00fe010000 - 0x00fe013fff] mem > PCI: 00:0d.0 10 <- [0x0000001000 - 0x00000010ff] io > PCI: 00:0d.0 14 <- [0x00fe019000 - 0x00fe0190ff] mem > PCI: 00:0f.0 10 <- [0x0000001cb0 - 0x0000001cb7] io > PCI: 00:0f.0 14 <- [0x0000001400 - 0x00000014ff] io > PCI: 00:0f.0 18 <- [0x0000001c00 - 0x0000001c3f] io > PCI: 00:0f.0 1c <- [0x0000001c80 - 0x0000001c9f] io > PCI: 00:0f.0 20 <- [0x0000001800 - 0x000000187f] io > PCI: 00:0f.0 24 <- [0x0000001c40 - 0x0000001c7f] io > PCI: 00:0f.2 20 <- [0x0000001ca0 - 0x0000001caf] io > PCI: 00:0f.3 10 <- [0x0000001880 - 0x00000018ff] io > PCI: 00:0f.4 10 <- [0x00fe016000 - 0x00fe016fff] mem > PCI: 00:0f.5 10 <- [0x00fe017000 - 0x00fe017fff] mem > PCI: 00:0f.6 10 <- [0x00fe014000 - 0x00fe015fff] mem > PCI: 00:0f.7 10 <- [0x00fe018000 - 0x00fe018fff] mem > PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 > Root Device assign_resources, bus 0 link: 0 > Done setting resources. > Done allocating resources. > Enabling resources... > PCI: 00:01.0 cmd <- 145 > PCI: 00:01.1 subsystem <- 00/00 > PCI: 00:01.1 cmd <- 142 > PCI: 00:01.2 cmd <- 142 > PCI: 00:0d.0 subsystem <- 00/00 > PCI: 00:0d.0 cmd <- 143 > cs5536: cs5536_pci_dev_enable_resources() > PCI: 00:0f.0 cmd <- 149 > PCI: 00:0f.2 cmd <- 141 > PCI: 00:0f.3 subsystem <- 00/00 > PCI: 00:0f.3 cmd <- 141 > PCI: 00:0f.4 subsystem <- 00/00 > PCI: 00:0f.4 cmd <- 142 > PCI: 00:0f.5 subsystem <- 00/00 > PCI: 00:0f.5 cmd <- 142 > PCI: 00:0f.6 cmd <- 142 > PCI: 00:0f.7 cmd <- 142 > done. > Initializing devices... > Root Device init > ARTECGROUP DBE61 ENTER init > Checking GPIO module... > DIVIL_LBAR_GPIO set to 0x0000f001 0x00001400 > ARTECGROUP DBE61 EXIT init > PCI: 00:01.0 init >>> Entering northbridge.c: northbridge_init > PCI: 00:01.1 init > PCI: 00:0d.0 init > PCI: 00:0f.0 init > cs5536: southbridge_init > RTC Init > GPIO_ADDR: 00001400 > cs5536: southbridge_init: enable_ide_nand_flash is 0 > PCI: 00:0f.2 init > cs5536_ide: ide_init > PCI: 00:0f.3 init > PCI: 00:0f.4 init > PCI: 00:0f.5 init > APIC_CLUSTER: 0 init >>> Entering northbridge.c: cpu_bus_init > malloc Enter, size 668, free_mem_ptr 000167d4 > malloc 0x000167d4 > Initializing CPU #0 > CPU: vendor AMD device 5a2 > CPU: family 05, model 0a, stepping 02 > model_lx_init > Enabling cache > A20 (0x92): 2 > A20 (0x92): 2 > CPU model_lx_init DONE > CPU #0 Initialized > PCI: 00:01.2 init > PCI: 00:0f.6 init > PCI: 00:0f.7 init > Devices initialized > Copying IRQ routing tables to 0xf0000...done. > Verifing copy of IRQ routing tables at 0xf0000...done > Checking IRQ routing table consistency... > check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 > /home/marcj/LinuxBIOSv2/src/arch/i386/boot/pirq_routing.c: > 36:check_pirq_routing_table() - checksum is: 0x00 but should be: 0xcc > done. > write_pirq_routing_table(8000785C, BABA) > PIR Entry 0 Dev/Fn: 8 Slot: 0 > INT: A bitmap: 400 PIRQ: 10 > INT: B bitmap: 0 PIRQ: 0 > INT: C bitmap: 0 PIRQ: 0 > INT: D bitmap: 0 PIRQ: 0 > Assigning IRQ 10 to 0:1.1 > Readback = 10 > pci_level_irq: current ints are 0x0 > pci_level_irq: try to set ints 0x400 > Assigning IRQ 10 to 0:1.2 > Readback = 10 > pci_level_irq: current ints are 0x400 > pci_level_irq: try to set ints 0x400 > PIR Entry 1 Dev/Fn: 78 Slot: 0 > INT: A bitmap: 400 PIRQ: 10 > INT: B bitmap: 800 PIRQ: 11 > INT: C bitmap: 400 PIRQ: 10 > INT: D bitmap: 800 PIRQ: 11 > Assigning IRQ 11 to 0:f.3 > Readback = 11 > pci_level_irq: current ints are 0x400 > pci_level_irq: try to set ints 0xc00 > Assigning IRQ 11 to 0:f.4 > Readback = 11 > pci_level_irq: current ints are 0xc00 > pci_level_irq: try to set ints 0xc00 > Assigning IRQ 11 to 0:f.5 > Readback = 11 > pci_level_irq: current ints are 0xc00 > pci_level_irq: try to set ints 0xc00 > PIR Entry 2 Dev/Fn: 68 Slot: 0 > INT: A bitmap: 400 PIRQ: 10 > INT: B bitmap: 0 PIRQ: 0 > INT: C bitmap: 0 PIRQ: 0 > INT: D bitmap: 0 PIRQ: 0 > Assigning IRQ 10 to 0:d.0 > Readback = 10 > pci_level_irq: current ints are 0xc00 > pci_level_irq: try to set ints 0xc00 > Moving GDT to 0x500...ok > Adjust low_table_end from 0x00000530 to 0x00001000 > Adjust rom_table_end from 0x000f0400 to 0x00100000 > Wrote linuxbios table at: 00000530 - 000006b4 checksum 8b3e > > Welcome to elfboot, the open sourced starter. > January 2002, Eric Biederman. > Version 1.3 > > rom_stream: 0xfff89000 - 0xfffeffff > Found ELF candidate at offset 0 > header_offset is 0 > Try to load at offset 0x0 > malloc Enter, size 32, free_mem_ptr 00016a70 > malloc 0x00016a70 > New segment addr 0x10000 size 0xfe60 offset 0x1000 filesize 0xfe60 > (cleaned up) New segment addr 0x10000 size 0xfe60 offset 0x1000 filesize > 0xfe60 > lb: [0x0000000000004000, 0x000000000001a000) > segment: [0x0000000000010000, 0x000000000001fe60, 0x000000000001fe60) > malloc Enter, size 32, free_mem_ptr 00016a90 > malloc 0x00016a90 > late: [0x000000000001a000, 0x000000000001fe60, 0x000000000001fe60) > bounce: [0x00000000077c0000, 0x00000000077ca000, 0x00000000077ca000) > Loading Segment: addr: 0x00000000077c0000 memsz: 0x000000000000a000 filesz: > 0x000000000000a000 > [ 0x00000000077c0000, 00000000077ca000, 0x00000000077ca000) <- > 0000000000001000 > > > ------------------------------------------------------------------------ > > Artec Group dbe61 mainboard support. > Now uses CAR. > New code for SPD-less memory implementation. > Updated IRQ routing. > > Signed-off-by: Marc Jones <[EMAIL PROTECTED]> > > Index: LinuxBIOSv2/src/mainboard/artecgroup/dbe61/auto.c > =================================================================== > --- LinuxBIOSv2.orig/src/mainboard/artecgroup/dbe61/auto.c 2007-06-18 > 17:34:59.000000000 -0600 > +++ /dev/null 1970-01-01 00:00:00.000000000 +0000 > @@ -1,134 +0,0 @@ > -#define ASSEMBLY 1 > - > -#include <stdint.h> > -#include <device/pci_def.h> > -#include <arch/io.h> > -#include <device/pnp_def.h> > -#include <arch/romcc_io.h> > -#include <arch/hlt.h> > -#include "pc80/serial.c" > -#include "arch/i386/lib/console.c" > -#include "ram/ramtest.c" > -//#include "superio/winbond/w83627hf/w83627hf_early_serial.c" > -#include "cpu/x86/bist.h" > -#include "cpu/x86/msr.h" > -#include <cpu/amd/lxdef.h> > - > -//#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) > - > -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" > -#include "southbridge/amd/cs5536/cs5536_early_setup.c" > - > -static inline int spd_read_byte(unsigned device, unsigned address) > -{ > - return smbus_read_byte(device, address); > -} > - > -#include "northbridge/amd/lx/raminit.h" > - > -static inline unsigned int fls(unsigned int x) > -{ > - int r; > - > - __asm__("bsfl %1,%0\n\t" > - "jnz 1f\n\t" > - "movl $32,%0\n" > - "1:" : "=r" (r) : "g" (x)); > - return r; > -} > - > -static void sdram_set_spd_registers(const struct mem_controller *ctrl) > -{ > - /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) > * > - * component Banks (byte 17) * module banks, side > (byte 5) * > - * width in bits (byte 6,7) > - * = Density per side (byte 31) * number of sides > (byte 5) */ > - /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now > */ > - msr_t msr; > - unsigned char module_banks, val; > - > - msr.hi = 0x10075012; > - msr.lo = 0x00000040; > - > - wrmsr(MC_CF07_DATA, msr); //GX3 > - > - /* timing and mode ... */ > - > - //msr = rdmsr(0x20000019); > - > - /* per standard bios settings */ > -/* > - msr.hi = 0x18000108; > - msr.lo = > - (6<<28) | // cas_lat > - (10<<24)| // ref2act > - (7<<20)| // act2pre > - (3<<16)| // pre2act > - (3<<12)| // act2cmd > - (2<<8)| // act2act > - (2<<6)| // dplwr > - (2<<4)| // dplrd > - (3); // dal > - * the msr value reported by quanta is very, very different. > - * we will go with that value for now. > - * > - //msr.lo = 0x286332a3; > -*/ > - //wrmsr(0x20000019, msr); //GX3 > - > -} > - > -#include "northbridge/amd/lx/raminit.c" > -#include "sdram/generic_sdram.c" > - > -/* CPU and GLIU mult/div */ > -#define PLLMSRhi 0x0000039C > -/* Hold Count - how long we will sit in reset */ > -#define PLLMSRlo 0x00DE0000 > - > -#include "northbridge/amd/lx/pll_reset.c" > -#include "cpu/amd/model_lx/cpureginit.c" > -#include "cpu/amd/model_lx/syspreinit.c" > - > -static void msr_init(void) > -{ > - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); > - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); > - > - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); > - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); > -} > - > - > -static void main(unsigned long bist) > -{ > - static const struct mem_controller memctrl [] = { > - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} > - }; > - > - SystemPreInit(); //GX3 OK > - > - msr_init(); //GX3 OK > - > - cs5536_early_setup(); //GX3 OK > - > - /* NOTE: must do this AFTER the early_setup! > - * it is counting on some early MSR setup > - * for cs5536 > - */ > - cs5536_setup_onchipuart(); //GX3 OK > - > - uart_init(); //GX3 OK > - console_init(); //GX3 OK > - > - pll_reset(); //GX3 OK > - > - cpuRegInit(); //GX3 OK > - > - print_err("done cpuRegInit\n"); > - > - sdram_initialize(1, memctrl); //GX3 OK almost > - > - /* Check all of memory */ > - //ram_check(0x00000000, 640*1024); > -} > Index: LinuxBIOSv2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c > =================================================================== > --- /dev/null 1970-01-01 00:00:00.000000000 +0000 > +++ LinuxBIOSv2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c > 2007-06-19 14:15:45.000000000 -0600 > @@ -0,0 +1,215 @@ > +/* > + * This file is part of the LinuxBIOS project. > + * > + * Copyright (C) 2007 Advanced Micro Devices, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#define ASSEMBLY 1 > + > +#include <stdint.h> > +#include <device/pci_def.h> > +#include <arch/io.h> > +#include <device/pnp_def.h> > +#include <arch/romcc_io.h> > +#include <arch/hlt.h> > +#include "pc80/serial.c" > +#include "arch/i386/lib/console.c" > +#include "ram/ramtest.c" > +#include "cpu/x86/bist.h" > +#include "cpu/x86/msr.h" > +#include <cpu/amd/lxdef.h> > +#include <cpu/amd/geode_post_code.h> > +#include "southbridge/amd/cs5536/cs5536.h" > +#include "spd_table.h" > + > + > +#define POST_CODE(x) outb(x, 0x80) > + > +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" > +#include "southbridge/amd/cs5536/cs5536_early_setup.c" > + > +#define DIMM0 0xA0 > +#define DIMM1 0xA2 > + > + > +static int spd_read_byte(unsigned device, unsigned address) > +{ > + int i; > + > + if (device == DIMM0){ > + for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){ > + if (spd_table[i].address == address){ > + return spd_table[i].data; > + } > + } > + } > + > + /* returns 0xFF on any failures */ > + return 0xFF; > +} > + > +#define ManualConf 0 /* Do automatic strapped PLL config */ > +/* CPU and GLIU mult/div 500/266*/ > +#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */ > +/* Hold Count - how long we will sit in reset */ > +#define PLLMSRlo 0x00DE6000 > + > +#include "northbridge/amd/lx/raminit.h" > +#include "northbridge/amd/lx/pll_reset.c" > +#include "northbridge/amd/lx/raminit.c" > +#include "sdram/generic_sdram.c" > +#include "cpu/amd/model_lx/cpureginit.c" > +#include "cpu/amd/model_lx/syspreinit.c" > + > +static void msr_init(void) > +{ > + msr_t msr; > + /* Setup access to the cache for under 1MB. */ > + msr.hi = 0x24fffc02; > + msr.lo = 0x1000A000; /* 0-A0000 write back */ > + wrmsr(CPU_RCONF_DEFAULT, msr); > + > + msr.hi = 0x0; /* write back */ > + msr.lo = 0x0; > + wrmsr(CPU_RCONF_A0_BF, msr); > + wrmsr(CPU_RCONF_C0_DF, msr); > + wrmsr(CPU_RCONF_E0_FF, msr); > + > + /* Setup access to the cache for under 640K. Note MC not setup yet. */ > + msr.hi = 0x20000000; > + msr.lo = 0xfff80; > + wrmsr(MSR_GLIU0 + 0x20, msr); > + > + msr.hi = 0x20000000; > + msr.lo = 0x80fffe0; > + wrmsr(MSR_GLIU0 + 0x21, msr); > + > + msr.hi = 0x20000000; > + msr.lo = 0xfff80; > + wrmsr(MSR_GLIU1 + 0x20, msr); > + > + msr.hi = 0x20000000; > + msr.lo = 0x80fffe0; > + wrmsr(MSR_GLIU1 + 0x21, msr); > + > +} > + > +static void mb_gpio_init(void) > +{ > + /* Early mainboard specific GPIO setup */ > +} > + > +static void cs5536_setup_onchipuart2(void) > +{ > + msr_t msr; > + > + /* GPIO4 - UART2_TX */ > + /* Set: Output Enable (0x4) */ > + outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); > + /* Set: OUTAUX1 Select (0x10) */ > + outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); > + /* GPIO4 - UART2_RX */ > + /* Set: Input Enable (0x20) */ > + outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); > + /* Set: INAUX1 Select (0x34) */ > + outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); > + > + /* Set: GPIO 3 + 3 Pull Up (0x18) */ > + outl(GPIOL_3_SET | GPIOL_4_SET, GPIO_IO_BASE + GPIOL_PULLUP_ENABLE); > + > + /* set address to 3F8 */ > + msr = rdmsr(MDD_LEG_IO); > + msr.lo |= 0x7 << 20; > + wrmsr(MDD_LEG_IO, msr); > + > + /* Bit 1 = DEVEN (device enable) > + * Bit 4 = EN_BANKS (allow access to the upper banks > + */ > + msr.lo = (1 << 4) | (1 << 1); > + msr.hi = 0; > + > + /* enable COM2 */ > + wrmsr(MDD_UART2_CONF, msr); > +} > + > +void cache_as_ram_main(void) > +{ > + POST_CODE(0x01); > + > + static const struct mem_controller memctrl[] = { > + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} > + }; > + > + SystemPreInit(); > + msr_init(); > + > + cs5536_early_setup(); > + > + /* NOTE: must do this AFTER the early_setup! > + * it is counting on some early MSR setup > + * for cs5536 > + */ > + /* cs5536_disable_internal_uart disable them. Set them up now... */ > + cs5536_setup_onchipuart2(); /* dbe61 uses UART2 as COM1 */ > + mb_gpio_init(); > + uart_init(); > + console_init(); > + > + pll_reset(ManualConf); > + > + cpuRegInit(); > + > + sdram_initialize(1, memctrl); > + > + /* Dump memory configuratation */ > + /*{ > + msr_t msr; > + msr = rdmsr(MC_CF07_DATA); > + print_debug("MC_CF07_DATA: "); > + print_debug_hex32(MC_CF07_DATA); > + print_debug(" value is: "); > + print_debug_hex32(msr.hi); > + print_debug(":"); > + print_debug_hex32(msr.lo); > + print_debug(" \n"); > + > + msr = rdmsr(MC_CF1017_DATA); > + print_debug("MC_CF1017_DATA: "); > + print_debug_hex32(MC_CF1017_DATA); > + print_debug(" value is: "); > + print_debug_hex32(msr.hi); > + print_debug(":"); > + print_debug_hex32(msr.lo); > + print_debug(" \n"); > + > + msr = rdmsr(MC_CF8F_DATA); > + print_debug("MC_CF8F_DATA: "); > + print_debug_hex32(MC_CF8F_DATA); > + print_debug(" value is: "); > + print_debug_hex32(msr.hi); > + print_debug(":"); > + print_debug_hex32(msr.lo); > + msr = rdmsr(MC_CF8F_DATA); > + print_debug(" \n"); > + }*/ > + > + /* Check memory. */ > + /* ram_check(0x00000000, 640 * 1024); */ > + > + /* Memory is setup. Return to cache_as_ram.inc and continue to boot */ > + return; > +} > Index: LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Config.lb > =================================================================== > --- LinuxBIOSv2.orig/src/mainboard/artecgroup/dbe61/Config.lb 2007-06-18 > 17:34:59.000000000 -0600 > +++ LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Config.lb 2007-06-18 > 17:38:31.000000000 -0600 > @@ -47,27 +47,17 @@ > if HAVE_PIRQ_TABLE object irq_tables.o end > #object reset.o > > -## > -## Romcc output > -## > -makerule ./failover.E > - depends "$(MAINBOARD)/failover.c ./romcc" > - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. > $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" > -end > > -makerule ./failover.inc > - depends "$(MAINBOARD)/failover.c ./romcc" > - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. > $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" > +if USE_DCACHE_RAM > + #compile cache_as_ram.c to auto.inc > + makerule ./cache_as_ram_auto.inc > + depends "$(MAINBOARD)/cache_as_ram_auto.c > option_table.h" > + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) > $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall > -c -S -o $@" > + action "perl -e 's/.rodata/.rom.data/g' -pi $@" > + action "perl -e 's/.text/.section .rom.text/g' -pi $@" > + end > end > > -makerule ./auto.E > - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" > - action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) > $(MAINBOARD)/auto.c -o $@" > -end > -makerule ./auto.inc > - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" > - action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) > $(MAINBOARD)/auto.c -o $@" > -end > > ## > ## Build our 16 bit and 32 bit linuxBIOS entry code > @@ -104,7 +94,7 @@ > ### > if USE_FALLBACK_IMAGE > ldscript /arch/i386/lib/failover.lds > - mainboardinit ./failover.inc > +# mainboardinit ./failover.inc > end > > ### > @@ -115,7 +105,11 @@ > ## Setup RAM > ## > mainboardinit cpu/x86/fpu/enable_fpu.inc > -mainboardinit ./auto.inc > + > +if USE_DCACHE_RAM > + mainboardinit cpu/amd/model_lx/cache_as_ram.inc > + mainboardinit ./cache_as_ram_auto.inc > +end > > ## > ## Include the secondary Configuration files > @@ -124,70 +118,44 @@ > config chip.h > > chip northbridge/amd/lx > - register "irqmap" = "0xcba5" > + device pci_domain 0 on > + device pci 1.0 on end # Northbridge > + device pci 1.1 on end # Graphics > + chip southbridge/amd/cs5536 > + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK > + # SIRQ Mode = Active(Quiet) mode. Save power.... > + # Invert mask = IRQ 12 and 1 are active high. Keyboard > and Mouse IRQs. OK > + register "lpc_serirq_enable" = "0x00001002" > + register "lpc_serirq_polarity" = "0x0000EFFD" > + register "lpc_serirq_mode" = "1" > + register "enable_gpio_int_route" = "0x0D0C0700" > + register "enable_ide_nand_flash" = "0" # 0:ide mode, > 1:flash > + register "enable_USBP4_device" = "0" #0: host, > 1:device > + register "enable_USBP4_overcurrent" = "0" #0:off, > xxxx:overcurrent setting CS5536 Data Book (pages 380-381) > + register "com1_enable" = "0" > + register "com1_address" = "0x2F8" > + register "com1_irq" = "3" > + register "com2_enable" = "1" > + register "com2_address" = "0x3F8" > + register "com2_irq" = "4" > + register "unwanted_vpci[0]" = "0" # End of list > has a zero > + device pci b.0 on end # Slot 3 > + device pci c.0 on end # Slot 4 > + device pci d.0 on end # Slot 1 > + device pci e.0 on end # Slot 2 > + device pci f.0 on end # ISA Bridge > + device pci f.2 on end # IDE Controller > + device pci f.3 on end # Audio > + device pci f.4 on end # OHCI > + device pci f.5 on end # EHCI > + end > + end > + # APIC cluster is late CPU init. > device apic_cluster 0 on > chip cpu/amd/model_lx > device apic 0 on end > end > end > - device pci_domain 0 on > > - device pci 1.0 on end # Host Bridge > - > -# chip drivers/pci/realmode > -# device pci 1.1 on end > # VGA > -# register "rom_address" = "0xfffc0000" # at the > beginning of 256k > -# end > - > - device pci 1.2 off end # AES > - chip southbridge/amd/cs5536_lx > - register "enable_ide_nand_flash" = "0" > - > - register "isa_irq" = "0" > - #register "flash_irq" = "14" > - > - ## IDE IRQ > - register "enable_ide_irq" = "0" > - > - register "audio_irq" = "5" > - register "usb_irq" = "7" > - > - register "uart0_irq" = "0" > - register "uart1_irq" = "4" > - > - ## PCI INTA ... INTD and their GPIO pins > - ## int==0: disable > - register "pci_int[0]" = "0" > - register "pci_int[1]" = "10" > - register "pci_int[2]" = "0" > - register "pci_int[3]" = "0" > - register "pci_int_pin[0]" = "0" > - register "pci_int_pin[1]" = "7" > - register "pci_int_pin[2]" = "0" > - register "pci_int_pin[3]" = "0" > > - > - > - # Keyboard Emulation Logic IRQs > - # Enable keyboard IRQ2 > - register "enable_kel_keyb_irq" = "0" > - # Enable mouse IRQ12 > - register "enable_kel_mouse_irq" = "0" > - # Configure KEL Emulation IRQ, 0 to disable > - register "kel_emul_irq" = "0" > - > - device pci f.0 on end # ISA Bridge > - device pci f.1 on end # Flash controller > - device pci f.2 off end # IDE controller > - device pci f.3 on end # Audio > - device pci f.4 on end # OHCI > - device pci f.5 on end # EHCI > - device pci f.6 off end # UDC controller > - device pci f.7 off end # OTG controller > - end > -# chip drivers/pci/rtl8139 > -## device pci d.0 on end # Realtek LAN > -# register "nic_irq" = "10" > -# end > - end > end > > Index: LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Options.lb > =================================================================== > --- LinuxBIOSv2.orig/src/mainboard/artecgroup/dbe61/Options.lb > 2007-06-18 17:34:59.000000000 -0600 > +++ LinuxBIOSv2/src/mainboard/artecgroup/dbe61/Options.lb 2007-06-19 > 15:14:51.000000000 -0600 > @@ -23,6 +23,7 @@ > uses CONFIG_ROM_PAYLOAD_START > uses CONFIG_COMPRESSED_PAYLOAD_LZMA > uses CONFIG_COMPRESSED_PAYLOAD_NRV2B > +uses CONFIG_PRECOMPRESSED_PAYLOAD > uses PAYLOAD_SIZE > uses _ROMBASE > uses _RAMBASE > @@ -44,6 +45,9 @@ > uses CONFIG_CONSOLE_VGA > uses CONFIG_PCI_ROM_RUN > uses CONFIG_VIDEO_MB > +uses USE_DCACHE_RAM > +uses DCACHE_RAM_BASE > +uses DCACHE_RAM_SIZE > > ## ROM_SIZE is the size of boot ROM that this board will use. > default ROM_SIZE = 256*1024 > @@ -51,8 +55,8 @@ > ### > ### Build options > ### > -default CONFIG_CONSOLE_VGA=1 > -default CONFIG_PCI_ROM_RUN=1 > +default CONFIG_CONSOLE_VGA=0 > +default CONFIG_PCI_ROM_RUN=0 > default CONFIG_VIDEO_MB=8 > > ## > @@ -78,8 +82,8 @@ > ## > ## Build code to export a programmable irq routing table > ## > -default HAVE_PIRQ_TABLE=0 > -default IRQ_SLOT_COUNT=6 > +default HAVE_PIRQ_TABLE=1 > +default IRQ_SLOT_COUNT=3 > > #object irq_tables.o > > @@ -97,6 +101,13 @@ > default FALLBACK_SIZE = 131072 > > ## > +## enable CACHE_AS_RAM specifics > +## > +default USE_DCACHE_RAM=1 > +default DCACHE_RAM_BASE=0xc8000 > +default DCACHE_RAM_SIZE=0x08000 > + > +## > ## Use a small 8K stack > ## > default STACK_SIZE=0x2000 > Index: LinuxBIOSv2/src/mainboard/artecgroup/dbe61/mainboard.c > =================================================================== > --- LinuxBIOSv2.orig/src/mainboard/artecgroup/dbe61/mainboard.c > 2007-06-18 17:34:59.000000000 -0600 > +++ LinuxBIOSv2/src/mainboard/artecgroup/dbe61/mainboard.c 2007-06-18 > 17:38:31.000000000 -0600 > @@ -1,3 +1,22 @@ > +/* > +* This file is part of the LinuxBIOS project. > +* > +* Copyright (C) 2007 Advanced Micro Devices > +* > +* This program is free software; you can redistribute it and/or modify > +* it under the terms of the GNU General Public License version 2 as > +* published by the Free Software Foundation. > +* > +* This program is distributed in the hope that it will be useful, > +* but WITHOUT ANY WARRANTY; without even the implied warranty of > +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +* GNU General Public License for more details. > +* > +* You should have received a copy of the GNU General Public License > +* along with this program; if not, write to the Free Software > +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > +*/ > + > #include <console/console.h> > #include <device/device.h> > #include <device/pci.h> > @@ -6,20 +25,15 @@ > #include <arch/io.h> > #include <cpu/x86/msr.h> > #include <cpu/amd/lxdef.h> > +#include "../../../southbridge/amd/cs5536/cs5536.h" > #include "chip.h" > > -#define DIVIL_LBAR_GPIO 0x5140000c > - > static void init_gpio() > { > msr_t msr; > - printk_debug("Initializing GPIO module...\n"); > + printk_debug("Checking GPIO module...\n"); > > - // initialize the GPIO LBAR > - msr.lo = GPIO_BASE; > - msr.hi = 0x0000f001; > - wrmsr(DIVIL_LBAR_GPIO, msr); > - msr = rdmsr(DIVIL_LBAR_GPIO); > + msr = rdmsr(MDD_LBAR_GPIO); > printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo); > } > > Index: LinuxBIOSv2/src/mainboard/artecgroup/dbe61/spd_table.h > =================================================================== > --- /dev/null 1970-01-01 00:00:00.000000000 +0000 > +++ LinuxBIOSv2/src/mainboard/artecgroup/dbe61/spd_table.h 2007-06-19 > 15:03:31.000000000 -0600 > @@ -0,0 +1,53 @@ > +/* > + * This file is part of the LinuxBIOS project. > + * > + * Copyright (C) 2007 Advanced Micro Devices, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#include <spd.h> > + > +struct spd_entry { > + unsigned int address; > + unsigned int data; > + }; > + > +/* Save space by using a short list of SPD values used by Geode LX Memory > init */ > +/* 128MB */ > +const struct spd_entry spd_table [] = > +{ > +{SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */ > +{SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */ > +{SPD_NUM_COLUMNS, 0x09}, /* Number of column address > bits */ > +{SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows > (banks) */ > +{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x50}, /* SDRAM cycle time (highest > CAS latency), RAS access time (tRAC) */ > +{SPD_REFRESH, 0x82}, /* Refresh rate/type */ > +{SPD_PRIMARY_SDRAM_WIDTH, 0x08}, /* SDRAM width (primary SDRAM) > */ > +{SPD_NUM_BANKS_PER_SDRAM, 0x04}, /* SDRAM device attributes, > number of banks on SDRAM device */ > +{SPD_ACCEPTABLE_CAS_LATENCIES, 0x1C}, /* SDRAM device attributes, CAS > latency */ > +{SPD_MODULE_ATTRIBUTES, 0x20}, /* SDRAM module attributes */ > +{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xC0}, /* SDRAM device attributes, > general */ > +{SPD_SDRAM_CYCLE_TIME_2ND, 0x60}, /* SDRAM cycle time (2nd > highest CAS latency) */ > +{SPD_SDRAM_CYCLE_TIME_3RD, 0x75}, /* SDRAM cycle time (3rd > highest CAS latency) */ > +{SPD_MIN_ROW_PRECHARGE_TIME, 0x3C}, /* Minimum row precharge time > (Trp) */ > +{SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x28}, /* Minimum row active to row > active (Trrd) */ > +{SPD_MIN_RAS_TO_CAS_DELAY, 0x3C}, /* Minimum RAS to CAS delay > (Trcd) */ > +{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x28}, /* Minimum RAS pulse width > (Tras) */ > +{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on > module */ > +{SPD_CMD_SIGNAL_INPUT_HOLD_TIME, 0x60}, /* Command and address signal > input hold time */ > +{SPD_tRC, 0x37}, /* SDRAM Device Minimum Active > to Active/Auto Refresh Time (tRC) */ > +{SPD_tRFC, 0x46} /* SDRAM Device Minimum Auto > Refresh to Active/Auto Refresh (tRFC) */ > +}; > Index: LinuxBIOSv2/targets/artecgroup/dbe61/Config.lb > =================================================================== > --- LinuxBIOSv2.orig/targets/artecgroup/dbe61/Config.lb 2007-06-18 > 17:34:59.000000000 -0600 > +++ LinuxBIOSv2/targets/artecgroup/dbe61/Config.lb 2007-06-18 > 17:38:31.000000000 -0600 > @@ -3,14 +3,21 @@ > target dbe61 > mainboard artecgroup/dbe61 > > +# HACK to get the right TSC support. > +option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 > + > option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 > +option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 > > ## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use > ## (normal AND fallback images and payloads). > -## leave 64k for vsa and 32K for video ROM > -option ROM_SIZE = 1024*256 - 64*1024 - 32 * 1024 > +## leave 36k for vsa and 32K for video ROM > +#option ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024 > + > +#No VGA for now > +option ROM_SIZE = 1024*512 - 36*1024 > > -## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS > image, > +# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS > image, > ## not including any payload. > option ROM_IMAGE_SIZE=64*1024 > > @@ -21,7 +28,7 @@ > romimage "fallback" > option USE_FALLBACK_IMAGE=1 > option LINUXBIOS_EXTRA_VERSION=".0Fallback" > - payload /tmp/filo.elf > + payload ../payload.elf > end > > -buildrom ./linuxbios.rom ROM_SIZE "fallback" > +buildrom ./dbe61.rom ROM_SIZE "fallback" > Index: LinuxBIOSv2/src/mainboard/artecgroup/dbe61/irq_tables.c > =================================================================== > --- LinuxBIOSv2.orig/src/mainboard/artecgroup/dbe61/irq_tables.c > 2007-06-19 15:46:39.000000000 -0600 > +++ LinuxBIOSv2/src/mainboard/artecgroup/dbe61/irq_tables.c 2007-06-19 > 15:14:08.000000000 -0600 > @@ -1,60 +1,105 @@ > -/* This file was generated by getpir.c, do not modify! > - (but if you do, please run checkpir on it to verify) > - * Contains the IRQ Routing Table dumped directly from your memory, which > BIOS sets up > +/* > + * This file is part of the LinuxBIOS project. > * > - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM > -*/ > + * Copyright (C) 2007 Advanced Micro Devices, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > > #include <arch/pirq_routing.h> > +#include <console/console.h> > +#include <arch/io.h> > +#include <arch/pirq_routing.h> > +#include "../../../southbridge/amd/cs5536/cs5536.h" > > -#define ID_SLOT_PCI_NET 1 // ThinCan > ethernet > -#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1 > -#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2 > -#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3 > -#define ID_EMBED_PCI 0xff // onboard PCI device > - > -// CS5535 PCI INT[A-D] Interrupt Routing lines. > -#define NO_CONNECT 0 // not used > -#define CS_PCI_INTA 1 // PCI INTA > -#define CS_PCI_INTB 2 // PCI INTB > -#define CS_PCI_INTC 3 // PCI INTC > -#define CS_PCI_INTD 4 // PCI INTD > - > -// IRQ bitmap reference line FEDCBA9876543210 > -// > 0000110000100000b > -#define PCI_IRQ 0xc20 // PCI allowed > IRQs here > - > -const struct irq_routing_table intel_irq_routing_table = > -{ > - PIRQ_SIGNATURE, /* u32 signature */ > - PIRQ_VERSION, /* u16 version */ > - 32+16*6, /* there can be total 2 devices on the bus */ > - 0x00, /* Where the interrupt router lies (bus) */ > - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ > - 0x0800, /* IRQs devoted exclusively to PCI usage */ > - 0x1022, /* Vendor */ > - 0x208f, /* Device */ > - 0x00000000, /* Crap (miniport) */ > - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ > - 0xdf, /* u8 checksum , this hase to set to some value that > would give 0 after the sum of all bytes for this structure (including > checksum) */ > +/* Platform IRQs */ > +#define PIRQA 10 > +#define PIRQB 11 > +#define PIRQC 10 > +#define PIRQD 11 > + > +/* Map */ > +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ > +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ > +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ > +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ > + > +/* Link */ > +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset > INTA# */ > +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset > INTB# */ > +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset > INTC# */ > +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset > INTD# */ > + > +const struct irq_routing_table intel_irq_routing_table = { > + PIRQ_SIGNATURE, /* u32 signature */ > + PIRQ_VERSION, /* u16 version */ > + 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the > bus */ > + 0x00, /* Where the interrupt router lies (bus) */ > + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ > + 0x00, /* IRQs devoted exclusively to PCI usage */ > + 0x100B, /* Vendor */ > + 0x002B, /* Device */ > + 0, /* Crap (miniport) */ > + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ > + 0x00, /* u8 checksum , this has to set to some > value that would give 0 after the sum of all bytes for this structure > (including checksum) */ > { > - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, > bitmap}, {link, bitmap}, slot, rfu */ > - // Geode GX3 Host Bridge and VGA Graphics > - {0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, > {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0}, > - // Realtek RTL8100/8139 Network Controller > - {0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, > {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0}, > - // Reserved for future extensions > - {0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, > {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0}, > - // Geode CS5535/CS5536 IO Companion: USB controllers, IDE, > Audio. > - {0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, > {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0}, > - // Reserved for future extensions > - {0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, > {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0}, > - // Reserved for future extensions > - {0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, > {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0} > - } > + /* If you change the number of entries, change the IRQ_SLOT_COUNT > above! */ > + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, > {link, bitmap}, {link, bitmap}, slot, rfu */ > + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, > 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ > + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, > {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ > + {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, > 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ > + } > }; > > unsigned long write_pirq_routing_table(unsigned long addr) > { > - return copy_pirq_routing_table(addr); > -} > + int i, j, k, num_entries; > + unsigned char pirq[4]; > + uint16_t chipset_irq_map; > + uint32_t pciAddr, pirtable_end; > + struct irq_routing_table *pirq_tbl; > + > + pirtable_end = copy_pirq_routing_table(addr); > + > + /* Set up chipset IRQ steering. */ > + pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; > + chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); > + printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, > + chipset_irq_map); > + outl(pciAddr & ~3, 0xCF8); > + outl(chipset_irq_map, 0xCFC); > + > + pirq_tbl = (struct irq_routing_table *)(addr); > + num_entries = (pirq_tbl->size - 32) / 16; > + > + /* Set PCI IRQs. */ > + for (i = 0; i < num_entries; i++) { > + printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, > + pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); > + for (j = 0; j < 4; j++) { > + printk_debug("INT: %c bitmap: %x ", 'A' + j, > + pirq_tbl->slots[i].irq[j].bitmap); > + for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) > & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in > bitmap to IRQ#. */ > + pirq[j] = k; > + printk_debug("PIRQ: %d\n", k); > + } > + > + /* Bus, device, slots IRQs for {A,B,C,D}. */ > + pci_assign_irqs(pirq_tbl->slots[i].bus, > + pirq_tbl->slots[i].devfn >> 3, pirq); > + } > + > + /* Put the PIR table in memory and checksum. */ > + return pirtable_end; > +} > \ No newline at end of file > -- Marc Jones Senior Software Engineer (970) 226-9684 Office mailto:[EMAIL PROTECTED] http://www.amd.com/embeddedprocessors -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios