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Hi again,
I'm attaching my ACPI/IRQ related files, ACPI on my machine works (I'm getting
power button events) and all IRQ are working too. I'm not supporting the PIC at
all.
You need to compile the dsdt.asl with iasl -tc and then rename it from dsdt.hex
to dsdt.c.
You need to have PMIO at 0x500 and free IRQ9.
Please consider those files as work in progress, they may lack correct copyright
header, or expose some no good mess ;) Good news is that they DO work.
I will release them all in some point in the future, now I'm fixing the AMD K8
DDR setup.
For example I dont know if vt8237_lpc.c is clean enough to be released? (I think
all it needs is just indent -kr -i8)
Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iD8DBQFG82Ug3J9wPJqZRNURAqwtAJ9Mm4mwNs6xX2/AHiI/LvC09iUIygCgjzUG
5SUdcLdIMBQSRWe7CW1fS1g=
=q9ho
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/*
* This file is part of the LinuxBIOS project.
*
* Based on other VIA SB code.
* Copyright (C) 2007 Rudolf Marek <[EMAIL PROTECTED]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License v2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include "vt8237r.h"
#include "chip.h"
#include <cpu/x86/lapic.h>
struct ioapicreg {
unsigned int reg;
unsigned int value_low, value_high;
};
extern void dump_south(device_t dev0);
static struct ioapicreg ioapicregvalues[] = {
#define ALL (0xff << 24)
#define NONE (0)
#define DISABLED (1 << 16)
#define ENABLED (0 << 16)
#define TRIGGER_EDGE (0 << 15)
#define TRIGGER_LEVEL (1 << 15)
#define POLARITY_HIGH (0 << 13)
#define POLARITY_LOW (1 << 13)
#define PHYSICAL_DEST (0 << 11)
#define LOGICAL_DEST (1 << 11)
#define ExtINT (7 << 8)
#define NMI (4 << 8)
#define SMI (2 << 8)
#define INT (1 << 8)
/* IO-APIC virtual wire mode configuration */
/* mask, trigger, polarity, destination, delivery, vector */
{ 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
{ 1, DISABLED, NONE},
{ 2, DISABLED, NONE},
{ 3, DISABLED, NONE},
{ 4, DISABLED, NONE},
{ 5, DISABLED, NONE},
{ 6, DISABLED, NONE},
{ 7, DISABLED, NONE},
{ 8, DISABLED, NONE},
{ 9, DISABLED, NONE},
{ 10, DISABLED, NONE},
{ 11, DISABLED, NONE},
{ 12, DISABLED, NONE},
{ 13, DISABLED, NONE},
{ 14, DISABLED, NONE},
{ 15, DISABLED, NONE},
{ 16, DISABLED, NONE},
{ 17, DISABLED, NONE},
{ 18, DISABLED, NONE},
{ 19, DISABLED, NONE},
{ 20, DISABLED, NONE},
{ 21, DISABLED, NONE},
{ 22, DISABLED, NONE},
{ 23, DISABLED, NONE},
/* Be careful and don't write past the end... */
};
static void setup_ioapic(unsigned long ioapic_base)
{
int i;
unsigned long value_low, value_high, adr;
volatile unsigned long *l;
struct ioapicreg *a = ioapicregvalues;
//delivered to CPU0
ioapicregvalues[0].value_high = (lapicid())<<(56-32);
l = (unsigned long *) ioapic_base;
l[0] = 3; //set APIC to FSB message
adr = l[4];
l[4] = (adr & 0xFFFFFE) | 1;
l[0] = 0; //set APIC ADDR - this will be APIC 2
adr = l[4];
l[4] = (adr & 0xF0FFFF) | (2<<24);
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;
value_low = l[4];
l[0] = (a->reg *2) + 0x11;
l[4] = a->value_high;
value_high = l[4];
if ((i==0) && (value_low == 0xffffffff)) {
printk_warning("IO APIC not responding.\n");
return;
}
printk_debug("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
a->reg, a->value_low, a->value_high);
}
}
static void pci_routing_fixup(struct device *dev)
{
/* set up PCI IRQ routing, route everything through APIC */
pci_write_config8(dev, 0x44, 0x00); /* PCI PNP Interrupt Routing INTE/F - disable */
pci_write_config8(dev, 0x45, 0x00); /* PCI PNP Interrupt Routing INTG/H - disable */
pci_write_config8(dev, 0x46, 0x10); /* Route INTE-INTH through registers above, no map to INTA-INTD */
pci_write_config8(dev, 0x54, 0x00); /* PCI Interrupt Polarity */
pci_write_config8(dev, 0x55, 0x00); /* PCI INTA# Routing */
pci_write_config8(dev, 0x56, 0x00); /* PCI INTB#/C# Routing */
pci_write_config8(dev, 0x57, 0x00); /* PCI INTD# Routing */
}
/*
* Set up the power management capabilities directly into ACPI mode. This
* avoids having to handle any System Management Interrupts (SMI's) which I
* can't figure out how to do !!!!
*/
void setup_pm(device_t dev)
{
// Set gen config 0
pci_write_config8(dev, 0x80, 0x20);
// Set ACPI base address to IO 0x500
pci_write_config16(dev, 0x88, 0x501);
// set ACPI irq to 9, need to set IRQ 9 override to level!
pci_write_config8(dev, 0x82, 0x49);
// primary interupt channel
pci_write_config16(dev, 0x84, 0x30b2);
// throttle / stop clock control
pci_write_config8(dev, 0x8d, 0x18);
pci_write_config8(dev, 0x93, 0x88);
pci_write_config8(dev, 0x94, 0xa4);
pci_write_config8(dev, 0x95, 0xcc);
pci_write_config8(dev, 0x98, 0);
pci_write_config8(dev, 0x99, 0x1e); //??
/* enable SATA LED, disable CPU Frequency Change */
pci_write_config8(dev, 0xe5, 0x9);
/* REQ5 as PCI request input - should be together with INTE-INTH*/
pci_write_config8(dev, 0xe4, 0x4);
// Enable ACPI access (and setup like award)
pci_write_config8(dev, 0x81, 0x84);
outw(0xffff, 0x500);
outw(0xffff, 0x520);
outw(0xffff, 0x528);
outl(0xffffffff, 0x530);
outw(0x0, 0x524);
outw(0x0, 0x52a);
outw(0x0, 0x52c);
outl(0x0, 0x534);
outl(0x0, 0x538); //fix
outb(0x0, 0x542);
outw(0x001, 0x504);
}
static void vt8237r_init(struct device *dev)
{
unsigned char enables, byte;
printk_debug("vt8237r init\n");
byte = pci_read_config8(dev, PCI_COMMAND);
byte |= PCI_COMMAND_WAIT;
pci_write_config8(dev, PCI_COMMAND, byte);
// enable the internal I/O decode
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
//FIXME Map 4MB of FLASH into the address space
pci_write_config8(dev, 0x41, 0x0);
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
enables = pci_read_config8(dev, 0x40);
enables |= 0x44;
pci_write_config8(dev, 0x40, enables);
// Set 0x42 to 0xf8 to match Award bios
enables = pci_read_config8(dev, 0x42);
enables |= 0xf8;
pci_write_config8(dev, 0x42, enables);
/* Delay Transaction Control */
pci_write_config8(dev, 0x43, 0xb);
/* IO Recovery time */
pci_write_config8(dev, 0x4c, 0x44);
/* ROM Memory Cycles Go To LPC */
pci_write_config8(dev, 0x59, 0x80);
/* bypass Bypass APIC De-Assert Message, INTE#, INTF#, INTG#, INTH# as PCI */
pci_write_config8(dev, 0x5B, 0xb);
/* set Read Pass Write Control Enable (force A2 from APIC FSB to low)*/
pci_write_config8(dev, 0x48, 0x8c);
/* Set 0x58 to 0x43 APIC and RTC*/
pci_write_config8(dev, 0x58, 0x43);
/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
//pci_write_config8(dev, 0x4f, enables);
/* enable serial irq */
pci_write_config8(dev, 0x52, 0x9);
/* dma */
//pci_write_config8(dev, 0x53, 0x00);
//enable HPET, ACPI has define to fixed addr
#define HPET_ADDR 0xfed00000ULL
pci_write_config16(dev, 0x69, ((HPET_ADDR >> 10) & 0xffff) );
pci_write_config8(dev, 0x6b, ((HPET_ADDR >> 26) & 0x3f) );
pci_write_config8(dev, 0x68, 0x80);
// Power management setup
setup_pm(dev);
// Start the rtc
rtc_init(0);
}
void vt8237r_read_resources(device_t dev)
{
struct resource *res;
pci_dev_read_resources(dev);
/* fixed APIC resource */
res = new_resource(dev, 0x44);
res->base = 0xfec00000;
res->size = 256;
res->limit = res->base + res->size -1;
res->align = 8;
res->gran = 8;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
void vt8237r_enable_resources(device_t dev)
{
/* vt8237r is not a pci bridge and has no resources of its own (other than standard PC i/o addresses)
however it does control the isa bus and so we need to manually call enable childrens resources on that bus */
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
static void keyboard_on(struct device *dev)
{
unsigned char regval;
regval = pci_read_config8(dev, 0x51);
regval |= 0x05;
regval &= 0xfd;
pci_write_config8(dev, 0x51, regval);
init_pc_keyboard(0x60, 0x64, 0);
}
static void southbridge_init(struct device *dev)
{
unsigned int v;
vt8237r_init(dev);
pci_routing_fixup(dev);
setup_ioapic(0xfec00000);
setup_i8259();
keyboard_on(dev);
//dump_south(dev);
}
static struct device_operations vt8237r_lpc_ops = {
.read_resources = vt8237r_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = vt8237r_enable_resources,
.init = &southbridge_init,
.scan_bus = scan_static_bus,
};
static struct pci_driver lpc_driver __pci_driver = {
.ops = &vt8237r_lpc_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = 0x3227,
};
/*
* LinuxBIOS ACPI Table support
* written by Stefan Reinauer <[EMAIL PROTECTED]>
* ACPI FADT, FACS, and DSDT table support added by
* Nick Barker <[EMAIL PROTECTED]>, and those portions
* (C) Copyright 2004 Nick Barker
* (C) Copyright 2005 Stefan Reinauer
*/
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci_ids.h>
extern unsigned char AmlCode[];
unsigned long acpi_fill_mcfg(unsigned long current)
{
device_t dev;
struct resource *res;
dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x5238, 0);
if (dev) {
res = find_resource(dev, 0x61);
if (res) {
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, res->base, 0x0, 0x0, 0xff);
}
}
return current;
}
unsigned long acpi_fill_madt(unsigned long current)
{
unsigned int gsi_base=0x18;
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write SB IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 0x2,
0xfec00000UL, 0);
/* Write NB IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 0x3,
0xfecc0000UL, gsi_base);
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); //IRQ9 ACPI active low
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0x0); //IRQ0 -> APIC IRQ2
/* create all subtables for processors */
current = acpi_create_madt_lapic_nmis(current, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
return current;
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_srat_t *srat;
acpi_rsdt_t *rsdt;
acpi_mcfg_t *mcfg;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
/* Align ACPI tables to 16byte */
start = ( start + 0x0f ) & -0x10;
current = start;
printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt);
acpi_write_rsdt(rsdt);
/*
* We explicitly add these tables later on:
*/
printk_debug("ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
dsdt = (acpi_header_t *)current;
current += ((acpi_header_t *)AmlCode)->length;
memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length);
dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
printk_debug("ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt,facs,dsdt);
acpi_add_table(rsdt,fadt);
printk_debug("ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdt,hpet);
/* If we want to use HPET Timers Linux wants an MADT */
printk_debug("ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current+=madt->header.length;
acpi_add_table(rsdt,madt);
printk_debug("ACPI: * MCFG\n");
mcfg = (acpi_mcfg_t *) current;
acpi_create_mcfg(mcfg);
current+=mcfg->header.length;
acpi_add_table(rsdt, mcfg);
/* SRAT */
printk_debug("ACPI: * SRAT\n");
srat = (acpi_srat_t *) current;
acpi_create_srat(srat);
current+=srat->header.length;
acpi_add_table(rsdt,srat);
printk_info("ACPI: done.\n");
return current;
}
/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2006 AMD
* Written by Yinghai Lu <[EMAIL PROTECTED]> for AMD.
*
* Copyright (C) 2006 MSI
* Written by Bingxun Shi <[EMAIL PROTECTED]> for MSI.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __ROMCC__
//#define K8_ALLOCATE_IO_RANGE 1
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
//used by raminit
#define QRANK_DIMM_SUPPORT 1
//used by init_cpus and fidvid
#define K8_SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#define DEBUG_SMBUS 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
#include <device/pci_ids.h>
//#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "sdram/generic_sdram.c"
/* msi does not want the default */
//#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
//#define MCP55_NUM 1
//#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
//set GPIO to input mode
//#define MCP55_MB_SETUP \
// RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
// RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
// RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
// RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
//#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
void activate_spd_rom(const struct mem_controller *ctrl)
{
}
void hard_reset(void)
{
/* nothing to do */
print_info("NO HARD RESET FIX ME!\n");
}
void soft_reset(void)
{
uint8_t tmp;
set_bios_reset();
print_info("soft reset \r\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
tmp |= 0x01;
pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
// mdelay(10);
/* PCI reset done */
tmp &=~1;
pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
// outb(0x02, 0x0cf9);
// outb(0x06, 0x0cf9); /* this value will assert RESET_L and LDTRST_L */
print_info("soft reset done\r\n");
}
unsigned get_sbdn(unsigned bus)
{
device_t dev;
/* Find the device.
* There can only be one 8111 on a hypertransport chain/bus.
*/
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_VIA, 0x3227),
bus);
return (dev>>15) & 0x1f;
}
#if USE_FALLBACK_IMAGE == 1
//#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
//#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
// byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
// byte |= 0x20;
// pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
// dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
// dword |= (1<<0);
// pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
}
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
// unsigned last_boot_normal_x = last_boot_normal();
//FIXME
unsigned last_boot_normal_x = 1;
// print_info("failover process\r\n");
u8 reg;
pnp_enter_ext_func_mode(SERIAL_DEV);
reg = pnp_read_config(SERIAL_DEV, 0x24);
pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); /* we have 24MHz input */
reg = pnp_read_config(SERIAL_DEV, 0x2A);
pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1)); /* we have GPIO for KB/MS PIN */
reg = pnp_read_config(SERIAL_DEV, 0x2C);
pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0)); /* we have all RESTOUT and even some reserved bits too */
pnp_exit_ext_func_mode(SERIAL_DEV);
pnp_enter_ext_func_mode(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV);
pnp_write_config(GPIO_DEV, 0xe0, 0xde); // 1101110 0=output 1=input
pnp_write_config(GPIO_DEV, 0xe1, 0x1); //set output val
pnp_write_config(GPIO_DEV, 0xe2, 0x0); //no inversion
pnp_write_config(GPIO_DEV, 0xe3, 0x3); //0000 0011 0=output 1=input
pnp_write_config(GPIO_DEV, 0xe4, 0xa4); //set output val
pnp_write_config(GPIO_DEV, 0xe5, 0x0); //no inversion
pnp_write_config(GPIO_DEV, 0x30, 0x9); //Enable GPIO 2 & GPIO 5
pnp_exit_ext_func_mode(GPIO_DEV);
w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
print_info("now booting... fallback\r\n");
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
// /* Setup the mcp55 */
// vt8237_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
//print_info("JMP normal image\r\n");
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
unsigned bsp_apicid = 0;
int needs_reset;
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
char *p ;
u8 reg;
//move CPU INIT back here
pnp_enter_ext_func_mode(SERIAL_DEV);
reg = pnp_read_config(SERIAL_DEV, 0x24);
pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); /* we have 24MHz input */
reg = pnp_read_config(SERIAL_DEV, 0x2A);
pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1)); /* we have GPIO for KB/MS PIN */
reg = pnp_read_config(SERIAL_DEV, 0x2C);
pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0)); /* we have all RESTOUT and even some reserved bits too */
pnp_exit_ext_func_mode(SERIAL_DEV);
pnp_enter_ext_func_mode(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV);
pnp_write_config(GPIO_DEV, 0xe0, 0xde); // 1101110 0=output 1=input
pnp_write_config(GPIO_DEV, 0xe1, 0x1); //set output val
pnp_write_config(GPIO_DEV, 0xe2, 0x0); //no inversion
pnp_write_config(GPIO_DEV, 0xe3, 0x3); //0000 0011 0=output 1=input
pnp_write_config(GPIO_DEV, 0xe4, 0xa4); //set output val
//0x10 seems to control something with SGD VIA
pnp_write_config(GPIO_DEV, 0xe5, 0x0); //no inversion
pnp_write_config(GPIO_DEV, 0x30, 0x9); //Enable GPIO 2 & GPIO 5
pnp_exit_ext_func_mode(GPIO_DEV);
w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
print_info("now booting... real_main\r\n");
if (bist == 0) {
//init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
// enable_lapic();
init_timer();
print_info("now booting... after init_cpus\r\n");
mdelay(1000);
print_info("now booting... after udelay\r\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/*
{
int i;
unsigned long tmp;
for (i=0;i<32;i++) {
tmp = pci_read_config16(PCI_DEV(0, 0x18, 1), 0x60);
print_debug_hex16(i);
print_debug_hex16(tmp);
tmp = pci_read_config16(PCI_DEV(0, 0x18, 1), 0x0);
print_debug_hex16(i);
print_debug_hex16(tmp);
// print_debug("WRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTENWRITTEN\n");
}
}
*/
print_info("now booting... bist\r\n");
// setup_a8v_resource_map();
setup_default_resource_map();
print_info("now booting... resource map\r\n");
setup_coherent_ht_domain();
print_info("now booting... HT domain\r\n");
wait_all_core0_started();
print_info("now booting... Core0 started\r\n");
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
//wait_all_other_cores_started(bsp_apicid);
#endif
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
print_info("now booting... htchains x\r\n");
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
// needs_reset |= mcp55_early_setup_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
//It's the time to set ctrl now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
memreset_setup();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
/*
* Minimalist ACPI DSDT table for EPIA-M / MII
* (C) Copyright 2004 Nick Barker <[EMAIL PROTECTED]>
* (C) Rudolf Marek <[EMAIL PROTECTED]>
*
* ISA portions taken from QEMU acpi-dsdt.dsl
* GPLv2
*/
DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
{
/*
* Define the main processor
*/
Scope (\_PR)
{
Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
}
/* For now only define 2 power states:
* - S0 which is fully on
* - S5 which is soft off
* any others would involve declaring the wake up methods
*/
Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 })
Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 })
/* Root of the bus hierarchy */
Scope (\_SB)
{
/* top PCI device */
Device (PCI0)
{
Name (_HID, EisaId ("PNP0A03"))
Name (_ADR, 0x00)
Name (_UID, 0x00)
Name (_BBN, 0x00)
/* PCI Routing Table */
//aaa
Name (_PRT, Package () {
Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 },
//slot 0xB
Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 },
//Slot 0xC
Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 },
//Slot 0xD
Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
Package (0x04) { 0x000F0000, 0x01, 0x00, 0x14 },
//0xf SATA IRQ 20
Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 },
//0xf NAtive IDE IRQ 20
Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 },
//USB routing
Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 },
//AC97 MC97
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B },
//PCIE16 bridge IRQ27
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },
//PCIE bridge IRQ31
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 },
//IRQ36
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 },
//IRQ39
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B }
//IRQ43
})
Device (PEGG)
{
Name (_ADR, 0x00020000)
Name (_UID, 0x00)
Name (_BBN, 0x02)
Name (_PRT, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 },
//PCIE IRQ24-IRQ27
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
})
} //end of PCIEG
Device (PEX0)
{
Name (_ADR, 0x00030000)
Name (_UID, 0x00)
Name (_BBN, 0x03)
Name (_PRT, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C },
//PCIE IRQ28-IRQ31
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
})
} //end of PEX0
Device (PEX1)
{
Name (_ADR, 0x00030001)
Name (_UID, 0x00)
Name (_BBN, 0x04)
Name (_PRT, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 },
//PCIE IRQ32-IRQ35
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
})
} //end f PEX1
Device (PEX2)
{
Name (_ADR, 0x00030002)
Name (_UID, 0x00)
Name (_BBN, 0x05)
Name (_PRT, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 },
//PCIE IRQ36-IRQ39
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
})
} //end f PEX2
Device (PEX3)
{
Name (_ADR, 0x00030003)
Name (_UID, 0x00)
Name (_BBN, 0x06)
Name (_PRT, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 },
//PCIE IRQ40-IRQ43
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
})
} //end f PEX3
Device (ISA) {
Name (_ADR, 0x00110000)
/* Keyboard seems to be important for WinXP install */
Device (KBD)
{
Name (_HID, EisaId ("PNP0303"))
Method (_STA, 0, NotSerialized)
{
Return (0x0f)
}
Method (_CRS, 0, NotSerialized)
{
Name (TMP, ResourceTemplate ()
{
IO (Decode16,
0x0060, // Address Range Minimum
0x0060, // Address Range Maximum
0x01, // Address Alignment
0x01, // Address Length
)
IO (Decode16,
0x0064, // Address Range Minimum
0x0064, // Address Range Maximum
0x01, // Address Alignment
0x01, // Address Length
)
IRQNoFlags ()
{1}
})
Return (TMP)
}
}
/* PS/2 mouse */
Device (MOU)
{
Name (_HID, EisaId ("PNP0F13"))
Method (_STA, 0, NotSerialized)
{
Return (0x0f)
}
Method (_CRS, 0, NotSerialized)
{
Name (TMP, ResourceTemplate ()
{
IRQNoFlags () {12}
})
Return (TMP)
}
}
/* PS/2 floppy controller */
Device (FDC0)
{
Name (_HID, EisaId ("PNP0700"))
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
IRQNoFlags () {6}
DMA (Compatibility, NotBusMaster, Transfer8) {2}
})
Return (BUF0)
}
} //FD END
} //ISA END
} // End of PCI0
} // End of _SB
} // End of Definition Block
/* This file was generated by getpir.c, do not modify!
* (but if you do, please run checkpir on it to verify)
*
* Contains the IRQ Routing Table dumped directly from your
* memory, which BIOS sets up.
*
* Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
*/
#ifdef GETPIR
#include "pirq_routing.h"
#else
#include <arch/pirq_routing.h>
#endif
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*18, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x11<<3)|0x0, /* Where the interrupt router lies (dev) */
0x820, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */
0x596, /* Device */
0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xe3, /* u8 checksum. This has to be set to some
value that would give 0 after the sum of all
bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x0b<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x0c<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
{0x00,(0x0d<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
{0x00,(0x08<<3)|0x0, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x03, 0xdeb8}, {0x03, 0xdeb8}, {0x03, 0xdeb8}, {0x03, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x07<<3)|0x0, {{0x02, 0xdeb8}, {0x02, 0xdeb8}, {0x02, 0xdeb8}, {0x02, 0x0deb8}}, 0x0, 0x0},
{0x02,(0x00<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x4, 0x0},
{0x03,(0x00<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x5, 0x0},
{0x04,(0x00<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x6, 0x0},
{0x05,(0x00<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0},
{0x06,(0x00<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x7, 0x0},
{0x00,(0x0f<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x02<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x03<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x03<<3)|0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x03<<3)|0x2, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x03<<3)|0x3, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}
/* generatred by MPTable, version 2.0.15*/
/* as modified by RGM for LinuxBIOS */
#include <arch/smp/mpspec.h>
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";
static const char productid[12] = "A8V-E SE ";
struct mp_config_table *mc;
unsigned int conforms = 0;
int bus_isa = 42;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
/*Bus: Bus ID Type*/
smp_write_bus(mc, 0, "PCI ");
smp_write_bus(mc, 1, "PCI ");
smp_write_bus(mc, 2, "PCI ");
smp_write_bus(mc, 3, "PCI ");
smp_write_bus(mc, 4, "PCI ");
smp_write_bus(mc, 5, "PCI ");
smp_write_bus(mc, 6, "PCI ");
smp_write_bus(mc, bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
//fixme - this should be read out from NB
smp_write_ioapic(mc, 3, 0x20, 0xfecc0000);
/*I/O Ints: Type Polarity Trigger Bus ID/IRQ APIC ID/PIN#
INTA# => IRQ16
INTB# => IRQ17
INTC# => IRQ18
INTD# => IRQ19 T o
A C
IDE (Native Mode)/SATA IRQ & INTE => IRQ20 0:0f.0 pinB 0:0f.1 pinA
I
USB IRQ (all 5 functions) and INTF => IRQ21 0:10.0-4 0 1 A 2 3 B 4 C
AC'97 / MC'97 IRQ and INTG => IRQ22 0:11.5 C 0:11.6
LAN IRQ and INTH => IRQ23 - have not
*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, 0x2, 0x5);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, 0x2, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xa, 0x2, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xb, 0x2, 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, 0x2, 0x10); //IRQ16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, 0x2, 0x11); //IRQ17
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, 0x2, 0x12); //IRQ18
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, 0x2, 0x13); //IRQ19
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, 0x2, 0x11); //IRQ17
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, 0x2, 0x12); //IRQ18
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, 0x2, 0x13); //IRQ19
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, 0x2, 0x10); //IRQ16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, 0x2, 0x12); //IRQ18
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, 0x2, 0x13); //IRQ19
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, 0x2, 0x10); //IRQ16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, 0x2, 0x11); //IRQ17
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, 0x2, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, 0x2, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, 0x2, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, 0x2, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, 0x2, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, 0x2, 0x16);
//?
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, 0x3, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, 0x3, 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, 0x3, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, 0x3, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, 0x3, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, 0x3, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, 0x3, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, 0x3, 0x5);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, 0x3, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, 0x3, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, 0x3, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, 0x3, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, 0x3, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, 0x3, 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, 0x3, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, 0x3, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, 0x3, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, 0x3, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, 0x3, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, 0x3, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, 0x3, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
//printf_debug("Wrote the mp table end at: %p - %p\n",
// mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v);
}
--
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