Jonathan Sturges wrote: >>> Jonathan Sturges wrote: >>> Two additional questions about CS5530 IRQ steering: >>> 1) Comments from Uwe Hermann and Peter Stuge have indicated that it's >>> really better for the kernel to setup the steering registers. Why is this? >>> It sounds like the BIOS is a good place to set these. I assume that a >>> knowledgeable OS could change them if necessary? At the very least, it >>> does sound like we all agree that it's OK to have LB setup the steering >>> until Linux is fixed. >>> >>> 2) Question about irq_tables.c. Many of the CS5536 systems have a >>> write_pirq_routing_table() in irq_tables.c that sets the steering >>> registers. I'd like to be able to set the steering registers in CS5530 >>> systems too, but I'm not a software developer and I need some help. So in >>> src/mainboard/artecgroup/dbe61/irq_tables.c, you have: >>> /* Set up chipset IRQ steering. */ >>> pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; >>> chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); >>> printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, >>> chipset_irq_map); >>> outl(pciAddr & ~3, 0xCF8); >>> outl(chipset_irq_map, 0xCFC);My main question with this block of code is >>> what the two outl() calls are for. It looks like pciAddr gets the address >>> of the 0x5c steering register, and chipset_irq_map sets the right bits to >>> set all 4 PIRQ lines. But I'd expect to see the chipset_irq_map written to >>> pciAddr. >>> >>> As an alternative, Kenji Noguchi used this code block to set the registers >>> in a CS5530 system he's working on (posted 5-May-2007): >>> device_t pdev; >>> //CS5530A >>> pdev = dev_find_slot(0, (0x12 << 3) + 0); >>> pci_write_config8(pdev, 0x5c, 0xab); >>> pci_write_config8(pdev, 0x5d, 0x09); >>> >>> >>> This block makes more sense to me. Obviously the register values could be >>> set by >>> #defines, but it looks simpler to me. >>> >>> Bottom line is, before I implement IRQ steering for my CS5530 system, I >>> want to understand what the first code block is doing, and if (or why) it's >>> preferable over the 2nd code block. Any guidance is appreciated. >>> >>> thanks, >>> Jonathan >> >> >> outl(pciAddr & ~3, 0xCF8); >> outl(chipset_irq_map, 0xCFC) >> >> is basically the same as >> >> pci_write_config8(pdev, 0x5c, 0xab); >> pci_write_config8(pdev, 0x5d, 0x09); >> >> >> CFC/CF8 is the PCI config space. > > Ahhh... thanks Marc, that was the clarification I needed. > > With that in mind, that block of code should work directly with the CS5530 > after defining CHIPSET_DEV_NUM appropriately. What about '0x80000000', is > that a common base address applicable to all CS553x systems? > > thanks, > Jonathan
DEV_NUM should be a constant for the 5530. It is always hooked up on the same IDSEL. The 0x80000000 is standard for all i/o based PCI config accesses. It indicates that it is a config access and not just a normal PCI i/o access. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:[EMAIL PROTECTED] http://www.amd.com/embeddedprocessors -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios