On my K8 board (a8n5x), with your last two patches it still makes memtest86
hang. I had to revert to your old patch to get it working again.
In case that helps, this is a diff of HEAD + your old patch relative to HEAD
+ your two new patches, with some simplifications (weed out cosmetical or
obvious changes). If you tell me how it can be split or simplified further,
I can test different subsets of it.
Thank you
--
Robert Millan
<GPLv2> I know my rights; I want my phone call!
<DRM> What use is a phone call, if you are unable to speak?
(as seen on /.)
diff -x .svn -ur LinuxBIOSv2_with_new_ruik_patches_sent_to_the_list/src/northbridge/amd/amdk8/northbridge.c LinuxBIOSv2_with_old_ruik_patch_that_works_on_my_board/src/northbridge/amd/amdk8/northbridge.c
--- LinuxBIOSv2_with_new_ruik_patches_sent_to_the_list/src/northbridge/amd/amdk8/northbridge.c 2007-09-30 19:15:31.000000000 +0200
+++ LinuxBIOSv2_with_old_ruik_patch_that_works_on_my_board/src/northbridge/amd/amdk8/northbridge.c 2007-09-30 19:20:20.000000000 +0200
@@ -562,7 +562,7 @@
base |= (resource->base >> 8) & 0xffffff00;
base |= 3;
limit &= 0x00000048;
- limit |= (resource_end(resource) >> 8) & 0xffffff00;
+ limit |= ((resource->base + resource->size - 1) >> 8) & 0xffffff00;
limit |= (resource->index & 3) << 4;
limit |= (nodeid & 7);
f1_write_config32(reg + 0x4, limit);
diff -x .svn -ur LinuxBIOSv2_with_new_ruik_patches_sent_to_the_list/src/northbridge/amd/amdk8/raminit.c LinuxBIOSv2_with_old_ruik_patch_that_works_on_my_board/src/northbridge/amd/amdk8/raminit.c
--- LinuxBIOSv2_with_new_ruik_patches_sent_to_the_list/src/northbridge/amd/amdk8/raminit.c 2007-09-30 19:15:29.000000000 +0200
+++ LinuxBIOSv2_with_old_ruik_patch_that_works_on_my_board/src/northbridge/amd/amdk8/raminit.c 2007-09-30 19:20:26.000000000 +0200
@@ -324,7 +324,7 @@
* 001 = 2 Mem clocks after CAS# (Registered Dimms)
* [31:23] Reserved
*/
- PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0),
+ PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(1 << 0),
/* DRAM Config Low Register
* F2:0x90
* [ 0: 0] DLL Disable
@@ -395,12 +395,14 @@
* 111 = Oldest entry in DCQ can be bypassed 7 times
* [31:28] Reserved
*/
- PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000,
+ PCI_ADDR(0, 0x18, 2, 0x90), 0xc0000000,
+ (1 << 29)|
+ (1 << 28)|
(4 << 25)|(0 << 24)|
(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)|
(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)|
(2 << 14)|(0 << 13)|(0 << 12)|
- (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)|
+ (0 << 11)|(0 << 10)|(1 << 9)|(0 << 8)| //CHANGE DUAL DIMM ENABLE
(0 << 3) |(0 << 1) |(0 << 0),
/* DRAM Config High Register
* F2:0x94
@@ -1206,18 +1208,7 @@
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_UnBufDimm;
if (unbuffered) {
- if ((has_dualch) && (!is_cpu_pre_d0())) {
- dcl |= DCL_UnBufDimm; // | DCL_DualDIMMen;
-
- // | DCL_En2T; SET if you have non-equal DDR mem types
-
- if ((cpuid_eax(1) & 0x30) == 0x30) {
- /* CS[7:4] is copy of CS[3:0], should be set for 939 socket */
- dcl |= DCL_UpperCSMap;
- }
- } else {
- dcl |= DCL_UnBufDimm;
- }
+ dcl |= DCL_UnBufDimm;
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
#if 0
@@ -1902,47 +1893,77 @@
static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *param)
{
uint32_t dth;
-
+ unsigned clocks;
+ clocks = 1; /* AMD says hard code this */
dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
- dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
+ dth |= ((clocks - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
}
static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
{
uint32_t dth, dtl;
+ unsigned divisor;
unsigned latency;
unsigned clocks;
- int lat, mtype;
clocks = 0;
dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
+ divisor = param->divisor;
if (is_opteron(ctrl)) {
- mtype = 0; /* dual channel */
- } else if (is_registered(ctrl)) {
- mtype = 1; /* registered 64bit interface */
- } else {
- mtype = 2; /* unbuffered 64bit interface */
+ if (latency == DTL_CL_2) {
+ if (divisor == ((6 << 0) + 0)) {
+ /* 166Mhz */
+ clocks = 3;
+ }
+ else if (divisor > ((6 << 0)+0)) {
+ /* 100Mhz && 133Mhz */
+ clocks = 2;
+ }
+ }
+ else if (latency == DTL_CL_2_5) {
+ clocks = 3;
+ }
+ else if (latency == DTL_CL_3) {
+ if (divisor == ((6 << 0)+0)) {
+ /* 166Mhz */
+ clocks = 4;
+ }
+ else if (divisor > ((6 << 0)+0)) {
+ /* 100Mhz && 133Mhz */
+ clocks = 3;
+ }
+ }
}
-
- switch (latency) {
- case DTL_CL_2:
- lat = 0;
- break;
- case DTL_CL_2_5:
- lat = 1;
- break;
- case DTL_CL_3:
- lat = 2;
- break;
- default:
- die("Unknown LAT for Trwt");
+ else /* Athlon64 */ {
+ if (is_registered(ctrl)) {
+ if (latency == DTL_CL_2) {
+ clocks = 2;
+ }
+ else if (latency == DTL_CL_2_5) {
+ clocks = 3;
+ }
+ else if (latency == DTL_CL_3) {
+ clocks = 3;
+ }
+ }
+ else /* Unbuffered */{
+ if (latency == DTL_CL_2) {
+ clocks = 3;
+ }
+ else if (latency == DTL_CL_2_5) {
+ clocks = 4;
+ }
+ else if (latency == DTL_CL_3) {
+ clocks = 4;
+ }
+ }
}
+ clocks = 4;
- clocks = param->dtl_trwt[lat][mtype];
if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
die("Unknown Trwt\r\n");
}
@@ -1974,44 +1995,86 @@
static void set_read_preamble(const struct mem_controller *ctrl, const struct mem_param *param)
{
uint32_t dch;
+ unsigned divisor;
unsigned rdpreamble;
- int slots, i;
-
- slots = 0;
-
- for(i = 0; i < 4; i++) {
- if (ctrl->channel0[i]) {
- slots += 1;
+ divisor = param->divisor;
+ dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+ dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
+ rdpreamble = 0;
+ if (is_registered(ctrl)) {
+ if (divisor == ((10 << 1)+0)) {
+ /* 100Mhz, 9ns */
+ rdpreamble = ((9 << 1)+ 0);
+ }
+ else if (divisor == ((7 << 1)+1)) {
+ /* 133Mhz, 8ns */
+ rdpreamble = ((8 << 1)+0);
+ }
+ else if (divisor == ((6 << 1)+0)) {
+ /* 166Mhz, 7.5ns */
+ rdpreamble = ((7 << 1)+1);
+ }
+ else if (divisor == ((5 << 1)+0)) {
+ /* 200Mhz, 7ns */
+ rdpreamble = ((7 << 1)+0);
}
}
-
- /* map to index to param.rdpreamble array */
- if (is_registered(ctrl)) {
- i = 0;
- } else if (slots < 3) {
- i = 1;
- } else if (slots == 3) {
- i = 2;
- } else if (slots == 4) {
- i = 3;
- } else {
- die("Unknown rdpreamble for this nr of slots");
+ else {
+ int slots;
+ int i;
+ slots = 0;
+ for(i = 0; i < 4; i++) {
+ if (ctrl->channel0[i]) {
+ slots += 1;
+ }
+ }
+ if (divisor == ((10 << 1)+0)) {
+ /* 100Mhz */
+ if (slots <= 2) {
+ /* 9ns */
+ rdpreamble = ((9 << 1)+0);
+ } else {
+ /* 14ns */
+ rdpreamble = ((14 << 1)+0);
+ }
+ }
+ else if (divisor == ((7 << 1)+1)) {
+ /* 133Mhz */
+ if (slots <= 2) {
+ /* 7ns */
+ rdpreamble = ((7 << 1)+0);
+ } else {
+ /* 11 ns */
+ rdpreamble = ((11 << 1)+0);
+ }
+ }
+ else if (divisor == ((6 << 1)+0)) {
+ /* 166Mhz */
+ if (slots <= 2) {
+ /* 6ns */
+ rdpreamble = ((7 << 1)+0);
+ } else {
+ /* 9ns */
+ rdpreamble = ((9 << 1)+0);
+ }
+ }
+ else if (divisor == ((5 << 1)+0)) {
+ /* 200Mhz */
+ if (slots <= 2) {
+ /* 5ns */
+ rdpreamble = ((5 << 1)+0);
+ } else {
+ /* 5.5ns */
+ rdpreamble = ((5 << 1)+1);
+ }
+ }
}
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
- dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
- rdpreamble = param->rdpreamble[i];
-
if ((rdpreamble < DCH_RDPREAMBLE_MIN) || (rdpreamble > DCH_RDPREAMBLE_MAX)) {
die("Unknown rdpreamble");
}
-
dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
-
- print_err("RDPREAMBLE: \n");
- print_err_hex16(rdpreamble);
- print_err("\n");
}
static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
@@ -2045,7 +2108,7 @@
}
else {
/* 6ns */
- async_lat = 6;
+ async_lat = 7;
}
}
dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
Only in LinuxBIOSv2_with_old_ruik_patch_that_works_on_my_board/src/northbridge/amd/amdk8: raminit.c~
--
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