Please always post boot logs and debug output to the list, where it's
archived. We want to be able to read up on old posts, problems, patches,
discussions even in 5 five years from now...
If the size does not matter I will.
R.
LinuxBIOS-2.0.0_Fallback Ãt ÅÃj 23 22:10:56 CEST 2007 starting...
now booting... fallback
LinuxBIOS-2.0.0_Normal Ãt ÅÃj 23 22:10:39 CEST 2007 starting...
now booting... real_main
core0 started:
now booting... Core0 started
started ap apicid:
LinuxBIOS-2.0.0_Fallback Ãt ÅÃj 23 22:10:56 CEST 2007 starting...
now booting... fallback
LinuxBIOS-2.0.0_Normal Ãt ÅÃj 23 22:10:39 CEST 2007 starting...
now booting... real_main
core1: ---- {APICID = 01 NODEID = 00 COREID = 01} ---
01
SBLink=00
NC node|link=00
LDT width and speed for K8T890 was1106ht reset -
soft reset
LinuxBIOS-2.0.0_Fallback Ãt ÅÃj 23 22:10:56 CEST 2007 starting...
now booting... fallback
LinuxBIOS-2.0.0_Normal Ãt ÅÃj 23 22:10:39 CEST 2007 starting...
now booting... real_main
core0 started:
now booting... Core0 started
started ap apicid:
LinuxBIOS-2.0.0_Fallback Ãt ÅÃj 23 22:10:56 CEST 2007 starting...
now booting... fallback
LinuxBIOS-2.0.0_Normal Ãt ÅÃj 23 22:10:39 CEST 2007 starting...
now booting... real_main
core1: ---- {APICID = 01 NODEID = 00 COREID = 01} ---
01
SBLink=00
NC node|link=00
LDT width and speed for K8T890 was1106DIMM 50 OFFSET 00
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 80
After reset status: 0040
DIMM 50 OFFSET 01
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 08
After reset status: 0040
DIMM 50 OFFSET 02
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 07
After reset status: 0040
DIMM 50 OFFSET 03
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0d
After reset status: 0040
DIMM 50 OFFSET 04
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0a
After reset status: 0040
DIMM 50 OFFSET 05
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 02
After reset status: 0040
DIMM 50 OFFSET 06
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 40
After reset status: 0040
DIMM 50 OFFSET 07
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 50 OFFSET 08
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 04
After reset status: 0040
DIMM 50 OFFSET 09
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 50
After reset status: 0040
DIMM 50 OFFSET 0a
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 60
After reset status: 0040
DIMM 50 OFFSET 0b
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 50 OFFSET 0c
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 82
After reset status: 0040
DIMM 50 OFFSET 0d
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 08
After reset status: 0040
DIMM 50 OFFSET 0e
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 50 OFFSET 0f
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 01
After reset status: 0040
DIMM 50 OFFSET 10
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0e
After reset status: 0040
DIMM 50 OFFSET 11
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 04
After reset status: 0040
DIMM 50 OFFSET 12
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0c
After reset status: 0040
DIMM 50 OFFSET 13
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 01
After reset status: 0040
DIMM 50 OFFSET 14
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 02
After reset status: 0040
DIMM 50 OFFSET 15
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 20
After reset status: 0040
DIMM 50 OFFSET 16
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 50 OFFSET 17
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 60
After reset status: 0040
DIMM 50 OFFSET 18
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 70
After reset status: 0040
DIMM 50 OFFSET 19
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 50 OFFSET 1a
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 50 OFFSET 1b
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 3c
After reset status: 0040
DIMM 50 OFFSET 1c
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 28
After reset status: 0040
DIMM 50 OFFSET 1d
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 3c
After reset status: 0040
WA
Ram1.00
Ram2.00
DIMM 50 OFFSET 02
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 07
After reset status: 0040
DIMM 51 OFFSET 02
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 07
After reset status: 0040
DIMM 52 OFFSET 02
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Device Error
Read: 00
After reset status: 0040
DIMM 53 OFFSET 02
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Device Error
Read: 00
After reset status: 0040
DIMM 50 OFFSET 02
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 07
After reset status: 0040
DIMM 51 OFFSET 02
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 07
After reset status: 0040
DIMM 50 OFFSET 03
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0d
After reset status: 0040
DIMM 51 OFFSET 03
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0d
After reset status: 0040
DIMM 50 OFFSET 04
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0a
After reset status: 0040
DIMM 51 OFFSET 04
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0a
After reset status: 0040
DIMM 50 OFFSET 05
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 02
After reset status: 0040
DIMM 51 OFFSET 05
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 02
After reset status: 0040
DIMM 50 OFFSET 06
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 40
After reset status: 0040
DIMM 51 OFFSET 06
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 40
After reset status: 0040
DIMM 50 OFFSET 07
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 51 OFFSET 07
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 50 OFFSET 09
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 50
After reset status: 0040
DIMM 51 OFFSET 09
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 50
After reset status: 0040
DIMM 50 OFFSET 0b
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 51 OFFSET 0b
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 50 OFFSET 0d
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 08
After reset status: 0040
DIMM 51 OFFSET 0d
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 08
After reset status: 0040
DIMM 50 OFFSET 11
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 04
After reset status: 0040
DIMM 51 OFFSET 11
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 04
After reset status: 0040
DIMM 50 OFFSET 12
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0c
After reset status: 0040
DIMM 51 OFFSET 12
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0c
After reset status: 0040
DIMM 50 OFFSET 15
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 20
After reset status: 0040
DIMM 51 OFFSET 15
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 20
After reset status: 0040
DIMM 50 OFFSET 17
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 60
After reset status: 0040
DIMM 51 OFFSET 17
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 60
After reset status: 0040
DIMM 50 OFFSET 1a
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 51 OFFSET 1a
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 50 OFFSET 1b
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 3c
After reset status: 0040
DIMM 51 OFFSET 1b
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 3c
After reset status: 0040
DIMM 50 OFFSET 1c
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 28
After reset status: 0040
DIMM 51 OFFSET 1c
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 28
After reset status: 0040
DIMM 50 OFFSET 1d
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 3c
After reset status: 0040
DIMM 51 OFFSET 1d
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 3c
After reset status: 0040
DIMM 50 OFFSET 1e
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 28
After reset status: 0040
DIMM 51 OFFSET 1e
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 28
After reset status: 0040
DIMM 50 OFFSET 29
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 37
After reset status: 0040
DIMM 51 OFFSET 29
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 37
After reset status: 0040
DIMM 50 OFFSET 2a
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 41
After reset status: 0040
DIMM 51 OFFSET 2a
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 41
After reset status: 0040
DIMM 50 OFFSET 03
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0d
After reset status: 0040
DIMM 50 OFFSET 04
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0a
After reset status: 0040
DIMM 50 OFFSET 11
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 04
After reset status: 0040
DIMM 50 OFFSET 07
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
DIMM 50 OFFSET 06
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 40
After reset status: 0040
DIMM 50 OFFSET 05
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 02
After reset status: 0040
DIMM 50 OFFSET 03
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0d
After reset status: 0040
DIMM 50 OFFSET 15
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 20
After reset status: 0040
NB CAP REG:00001119
DIMM 50 OFFSET 12
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0c
After reset status: 0040
DIMM 50 OFFSET 17
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 60
After reset status: 0040
DIMM 50 OFFSET 09
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 50
After reset status: 0040
DIMM 50 OFFSET 12
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0c
After reset status: 0040
DIMM 50 OFFSET 09
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 50
After reset status: 0040
200Mhz
DIMM 50 OFFSET 29
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 37
After reset status: 0040
DIMM 50 OFFSET 2a
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 41
After reset status: 0040
DIMM 50 OFFSET 1d
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 3c
After reset status: 0040
DIMM 50 OFFSET 1c
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 28
After reset status: 0040
DIMM 50 OFFSET 1e
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 28
After reset status: 0040
DIMM 50 OFFSET 1b
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 3c
After reset status: 0040
DIMM 50 OFFSET 03
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 0d
After reset status: 0040
DIMM 50 OFFSET 0d
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 08
After reset status: 0040
DIMM 50 OFFSET 05
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 02
After reset status: 0040
DIMM 50 OFFSET 0b
After reset status: 0040
Waiting until smbus ready
Waiting until smbus ready
Read: 00
After reset status: 0040
RDPREAMBLE:
000a
Ram3
Initializing memory: done
Ram4
v_esp=000ceec8
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Copying LinuxBIOS to RAM.
src=fffa0000
dst=00004000
linxbios_ram.nrv2b length = 0000dc2a
linxbios_ram.bin length = 00021e40
Jumping to LinuxBIOS.
LinuxBIOS-2.0.0_Normal Ãt ÅÃj 23 22:10:39 CEST 2007 booting...
Enumerating buses...
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
PCI: 00:18.3 siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] enabled
In vt8237r_enable 1106 0238.
PCI: 00:00.0 [1106/0238] enabled
PCI: 00:00.0 [1106/0238] enabled next_unitid: 0013
PCI: pci_scan_bus for bus 00
In vt8237r_enable 1106 0238.
PCI: 00:00.0 [1106/0238] enabled
PCI: 00:00.1 [1106/1238] enabled
00: 06 11 38 22 06 00 00 02 00 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 80 00 31 30 08 00 86 7f cf 44 44 34 00 22 40
b0: 3f 13 00 00 03 00 00 00 00 00 00 00 00 00 00 00
c0: aa 00 aa 00 50 50 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Writeback to acfailed 34
00: 06 11 38 22 06 00 00 02 00 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 13 8e 0e 31 30 3c 80 86 7f cf 44 22 34 00 22 40
b0: 3f 13 00 00 02 00 00 00 00 00 00 00 00 00 00 00
c0: 20 aa aa 02 50 50 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:00.2 [1106/2238] enabled
PCI: 00:00.3 [1106/3238] enabled
PCI: 00:00.4 [1106/4238] enabled
PCI: 00:00.5 [1106/5238] enabled
PCI: 00:00.7 [1106/7238] enabled
PCI: 00:01.0 [1106/b188] enabled
Configuring PCIe PEG
00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00
40: 10 68 41 01 41 0e 00 00 00 00 10 00 01 0d 00 00
50: 00 00 01 01 60 00 00 00 00 00 48 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00
b0: 0c 12 40 80 00 00 03 00 00 00 00 00 00 00 00 00
c0: 03 00 01 00 44 44 44 44 44 44 44 44 00 00 00 00
d0: 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 0c 07 01 8a f8 00 00 00 01 82 f8 00 00 00 00 00
f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00
00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00
40: 10 68 41 01 41 0e 00 00 00 00 10 00 01 0d 00 00
50: 00 00 01 01 60 00 00 00 00 00 48 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 04 00 00 30 00 00 00 00 00 00 00 00 00 00 00
b0: 0c f0 40 80 00 00 03 00 01 00 00 00 00 00 00 00
c0: 43 00 01 00 44 44 44 44 44 44 44 44 00 00 00 00
d0: 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 0c 0b 01 8a f8 00 00 00 01 82 f8 00 00 00 00 00
f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:02.0 [1106/a238] enabled
Configuring PCIe PEXs
00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00
40: 10 68 41 01 01 0e 00 00 00 00 10 00 41 0c 00 01
50: 00 00 01 00 60 00 00 00 00 00 48 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00
b0: 3b 59 40 80 00 00 03 00 00 00 00 00 00 00 00 00
c0: 03 00 01 00 44 44 00 00 00 00 00 00 00 00 00 00
d0: 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 0b 01 8a f8 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00
00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00
40: 10 68 41 01 01 0e 00 00 00 00 10 00 41 0c 00 01
50: 00 00 01 00 60 00 00 00 00 00 48 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00
b0: 3b f0 40 80 00 00 03 00 00 00 00 00 00 00 00 00
c0: 03 00 01 00 44 44 00 00 00 00 00 00 00 00 00 00
d0: 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 0b 01 8a f8 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:03.0 [1106/c238] enabled
Configuring PCIe PEXs
00: 06 11 38 d2 00 00 10 00 00 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 02 00 00
40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 00 02
50: 00 00 01 00 60 00 00 00 00 00 48 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00
b0: 3b 59 40 80 00 00 03 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00
d0: 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00: 06 11 38 d2 00 00 10 00 00 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 02 00 00
40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 00 02
50: 00 00 01 00 60 00 00 00 00 00 48 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00
b0: 3b f0 40 80 00 00 03 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00
d0: 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:03.1 [1106/d238] enabled
Configuring PCIe PEXs
00: 06 11 38 e2 00 00 10 00 00 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 03 00 00
40: 10 68 41 01 c1 0e 00 00 00 00 10 00 11 0c 00 03
50: 00 00 11 00 60 00 00 00 00 00 48 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00
b0: 3b 59 40 80 00 00 03 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00
d0: 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00: 06 11 38 e2 00 00 10 00 00 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 03 00 00
40: 10 68 41 01 c1 0e 00 00 00 00 10 00 11 0c 00 03
50: 00 00 11 00 60 00 00 00 00 00 48 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00
b0: 3b f0 40 80 00 00 03 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00
d0: 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:03.2 [1106/e238] enabled
Configuring PCIe PEXs
00: 06 11 38 f2 00 00 10 00 00 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 04 00 00
40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 00 04
50: 00 00 01 00 60 00 00 00 00 00 48 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00
b0: 3b 59 40 80 00 00 03 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00
d0: 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00: 06 11 38 f2 00 00 10 00 00 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 04 00 00
40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 00 04
50: 00 00 01 00 60 00 00 00 00 00 48 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00
b0: 3b f0 40 80 00 00 03 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00
d0: 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:03.3 [1106/f238] enabled
PCI: 00:0c.0 [10ec/8139] enabled
PCI: 00:0f.0 [1106/3149] enabled
PCI: 00:0f.1 [1106/0571] enabled
PCI: 00:10.0 [1106/3038] enabled
PCI: 00:10.1 [1106/3038] enabled
PCI: 00:10.2 [1106/3038] enabled
PCI: 00:10.3 [1106/3038] enabled
PCI: 00:10.4 [1106/3104] enabled
PCI: 00:10.5 [1106/d104] enabled
In vt8237r_enable 1106 3227.
PCI: 00:11.0 [1106/3227] enabled
PCI: 00:11.5 [1106/3059] enabled
PCI: 00:11.6 [1106/3068] enabled
In vt8237r_enable ffff ffff.
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [1002/5b60] enabled
PCI: 02:00.1 [1002/5b70] enabled
PCI: pci_scan_bus returning with max=002
PCIEXP: tunning PCI: 02:00.0
PCIEXP: tunning PCI: 02:00.1
PCI: pci_scan_bus for bus 03
PCI: pci_scan_bus returning with max=003
PCI: pci_scan_bus for bus 04
PCI: pci_scan_bus returning with max=004
PCI: pci_scan_bus for bus 05
PCI: 05:00.0 [11ab/4362] enabled
PCI: pci_scan_bus returning with max=005
PCIEXP: tunning PCI: 05:00.0
PCI: pci_scan_bus for bus 06
PCI: pci_scan_bus returning with max=006
smbus: PCI: 00:11.0[0]->I2C: 01:50 enabled
smbus: PCI: 00:11.0[0]->I2C: 01:51 enabled
smbus: PCI: 00:11.0[0]->I2C: 01:52 enabled
smbus: PCI: 00:11.0[0]->I2C: 01:53 enabled
PNP: 002e.0 enabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 disabled
PNP: 002e.5 disabled
PNP: 002e.6 disabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
PNP: 002e.b enabled
PCI: pci_scan_bus returning with max=006
PCI: pci_scan_bus returning with max=006
done
Allocating resources...
Reading resources...
PCI: 00:01.0 1c <- [0x000000f000 - 0x000000efff] bus 01 io
PCI: 00:01.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 01 prefmem
PCI: 00:01.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 01 mem
PCI: 00:03.0 1c <- [0x000000f000 - 0x000000efff] bus 03 io
PCI: 00:03.0 24 <- [0x0ffff00000 - 0x0fffefffff] bus 03 prefmem
PCI: 00:03.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 03 mem
PCI: 00:03.1 1c <- [0x000000f000 - 0x000000efff] bus 04 io
PCI: 00:03.1 24 <- [0x0ffff00000 - 0x0fffefffff] bus 04 prefmem
PCI: 00:03.1 20 <- [0x00fff00000 - 0x00ffefffff] bus 04 mem
PCI: 00:03.2 24 <- [0x0ffff00000 - 0x0fffefffff] bus 05 prefmem
PCI: 00:03.3 1c <- [0x000000f000 - 0x000000efff] bus 06 io
PCI: 00:03.3 24 <- [0x0ffff00000 - 0x0fffefffff] bus 06 prefmem
PCI: 00:03.3 20 <- [0x00fff00000 - 0x00ffefffff] bus 06 mem
PCI: 00:10.5 register 10(ffffffff), read-only ignoring it
PCI: 00:10.5 register 14(ffffffff), read-only ignoring it
PCI: 00:10.5 register 18(ffffffff), read-only ignoring it
PCI: 00:10.5 register 1c(ffffffff), read-only ignoring it
PCI: 00:10.5 register 20(ffffffff), read-only ignoring it
PCI: 00:10.5 register 24(ffffffff), read-only ignoring it
PCI: 00:10.5 register 30(ffffffff), read-only ignoring it
Done reading resources.
Allocating VGA resource PCI: 02:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Setting resources...
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 1b8 <- [0x00c0000000 - 0x00d7ffffff] prefmem <node 0 link 0>
PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000004fff] io <node 0 link 0>
PCI: 00:18.0 1b0 <- [0x00e0000000 - 0x00f02fffff] mem <node 0 link 0>
PCI: 00:00.0 10 <- [0x00c0000000 - 0x00cfffffff] prefmem
PCI: 00:02.0 1c <- [0x0000001000 - 0x0000001fff] bus 02 io
PCI: 00:02.0 24 <- [0x00d0000000 - 0x00d7ffffff] bus 02 prefmem
PCI: 00:02.0 20 <- [0x00f0000000 - 0x00f00fffff] bus 02 mem
PCI: 02:00.0 10 <- [0x00d0000000 - 0x00d7ffffff] prefmem
PCI: 02:00.0 14 <- [0x0000001000 - 0x00000010ff] io
PCI: 02:00.0 18 <- [0x00f0020000 - 0x00f002ffff] mem
PCI: 02:00.0 30 <- [0x00f0000000 - 0x00f001ffff] romem
PCI: 02:00.1 10 <- [0x00f0030000 - 0x00f003ffff] mem
PCI: 00:03.2 1c <- [0x0000002000 - 0x0000002fff] bus 05 io
PCI: 00:03.2 20 <- [0x00f0100000 - 0x00f01fffff] bus 05 mem
PCI: 05:00.0 10 <- [0x00f0120000 - 0x00f0123fff] mem64
PCI: 05:00.0 18 <- [0x0000002000 - 0x00000020ff] io
PCI: 05:00.0 30 <- [0x00f0100000 - 0x00f011ffff] romem
PCI: 00:0c.0 10 <- [0x0000003000 - 0x00000030ff] io
PCI: 00:0c.0 14 <- [0x00f0210000 - 0x00f02100ff] mem
PCI: 00:0c.0 30 <- [0x00f0200000 - 0x00f020ffff] romem
PCI: 00:0f.0 10 <- [0x00000040a0 - 0x00000040a7] io
PCI: 00:0f.0 14 <- [0x00000040c0 - 0x00000040c3] io
PCI: 00:0f.0 18 <- [0x00000040b0 - 0x00000040b7] io
PCI: 00:0f.0 1c <- [0x00000040d0 - 0x00000040d3] io
PCI: 00:0f.0 20 <- [0x0000004080 - 0x000000408f] io
PCI: 00:0f.0 24 <- [0x0000003400 - 0x00000034ff] io
PCI: 00:0f.1 20 <- [0x0000004090 - 0x000000409f] io
PCI: 00:10.0 20 <- [0x0000004000 - 0x000000401f] io
PCI: 00:10.1 20 <- [0x0000004020 - 0x000000403f] io
PCI: 00:10.2 20 <- [0x0000004040 - 0x000000405f] io
PCI: 00:10.3 20 <- [0x0000004060 - 0x000000407f] io
PCI: 00:10.4 10 <- [0x00f0211000 - 0x00f02110ff] mem
PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] io
PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] irq
PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] drq
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] irq
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] io
PNP: 002e.b 70 <- [0x0000000000 - 0x0000000000] irq
PCI: 00:11.5 10 <- [0x0000003800 - 0x00000038ff] io
PCI: 00:11.6 10 <- [0x0000003c00 - 0x0000003cff] io
PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] mem <gart>
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 140
PCI: 00:00.0 cmd <- 146
PCI: 00:00.1 cmd <- 146
PCI: 00:00.2 cmd <- 146
PCI: 00:00.3 cmd <- 146
PCI: 00:00.4 cmd <- 146
PCI: 00:00.5 cmd <- 146
PCI: 00:00.7 cmd <- 146
PCI: 00:01.0 bridge ctrl <- 0017
PCI: 00:01.0 cmd <- 147
PCI: 00:02.0 bridge ctrl <- 000b
PCI: 00:02.0 cmd <- 147
PCI: 02:00.0 cmd <- 143
PCI: 02:00.1 cmd <- 142
PCI: 00:03.0 bridge ctrl <- 0003
PCI: 00:03.0 cmd <- 140
PCI: 00:03.1 bridge ctrl <- 0003
PCI: 00:03.1 cmd <- 140
PCI: 00:03.2 bridge ctrl <- 0003
PCI: 00:03.2 cmd <- 147
PCI: 05:00.0 cmd <- 143
PCI: 00:03.3 bridge ctrl <- 0003
PCI: 00:03.3 cmd <- 140
PCI: 00:0c.0 cmd <- 143
PCI: 00:0f.0 cmd <- 141
PCI: 00:0f.1 cmd <- 1c1
PCI: 00:10.0 cmd <- 141
PCI: 00:10.1 cmd <- 141
PCI: 00:10.2 cmd <- 141
PCI: 00:10.3 cmd <- 141
PCI: 00:10.4 cmd <- 142
PCI: 00:10.5 cmd <- ffff
PCI: 00:11.0 cmd <- 147
I2C: 01:50 missing enable_resources
I2C: 01:51 missing enable_resources
I2C: 01:52 missing enable_resources
I2C: 01:53 missing enable_resources
w83627ehg hwm smbus enabled
PCI: 00:11.5 cmd <- 141
PCI: 00:11.6 cmd <- 141
PCI: 00:18.1 subsystem <- 1462/9282
PCI: 00:18.1 cmd <- 140
PCI: 00:18.2 subsystem <- 1462/9282
PCI: 00:18.2 cmd <- 140
PCI: 00:18.3 cmd <- 140
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor AMD device 20f32
CPU: family 0f, model 23, stepping 02
Enabling cache
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
microcode: equivalent processor rev id = 0x0210, patch id = 0x00000000
microcode: patch id that want to apply= 0x0000004d
microcode: updated to patch id = 0x0000004d success
CPU model Dual Core AMD Opteron(tm) Processor 175
Setting up local apic... apic_id: 0x00 done.
ECC Disabled
CPU #0 Initialized
Asserting INIT. on 1
CPU 0x01 would not start!
CPU 0x01 did not initialize!
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:11.0 init
vt8237r init
RTC Init
PNP: 002e.0 init
PNP: 002e.2 init
PNP: 002e.b init
PCI: 00:18.1 init
PCI: 00:18.2 init
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:00.1 init
PCI: 00:00.4 init
PCI: 00:0c.0 init
rom address for PCI: 00:0c.0 = f0200000
Incorrect Expansion ROM Header Signature 0000
PCI: 00:0f.0 init
Configuring VIA SATA Controller
PCI: 00:0f.1 init
Enabling VIA IDE.
enables in reg 0x40 0x38
enables in reg 0x40 read back as 0x3b
ide_init: enabling compatibility IDE addresses
enables in reg 0x42 0x9
enables in reg 0x42 read back as 0x9
enables in reg 0x9 0x8a
enables in reg 0x9 read back as 0x8a
command in reg 0x4 0x81
command in reg 0x4 reads back as 0x85
PCI: 00:10.0 init
PCI: 00:10.1 init
PCI: 00:10.2 init
PCI: 00:10.3 init
PCI: 00:10.4 init
PCI: 00:10.5 init
PCI: 00:11.5 init
PCI: 00:11.6 init
PCI: 02:00.0 init
rom address for PCI: 02:00.0 = f0000000
copying VGA ROM Image from 0xf0000000 to 0xc0000, 0x10000 bytes
entering emulator
halt_sys: file
/home/ruik/Moje_dilna/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c, line 4387
PCI: 02:00.1 init
PCI: 05:00.0 init
rom address for PCI: 05:00.0 = f0100000
Incorrect Expansion ROM Header Signature ffff
Devices initialized
Copying IRQ routing tables to 0xf0000...done.
Verifing copy of IRQ routing tables at 0xf0000...done
Checking IRQ routing table consistency...
Inconsistent IRQ routing table size (0xd0/0x140)
check_pirq_routing_table() - irq_routing_table located at: 0x000f0000
/home/ruik/Moje_dilna/LinuxBIOSv2/src/arch/i386/boot/pirq_routing.c:
36:check_pirq_routing_table() - checksum is: 0xe3 but should be: 0xf1
done.
ACPI: Writing ACPI tables at f0400...
ACPI: * FACS
ACPI: * DSDT @ 000f04ae Length 44e
ACPI: * FADT
ACPI: added table 1/9 Length now 40
ACPI: * HPET
ACPI: added table 2/9 Length now 44
ACPI: * MADT
ACPI: added table 3/9 Length now 48
ACPI: * MCFG
ACPI: added table 4/9 Length now 52
ACPI: * SRAT
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000,
sizek=00000280
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300,
sizek=000ffd00
ACPI: added table 5/9 Length now 56
ACPI: done.
Moving GDT to 0x500...ok
Adjust low_table_end from 0x00000530 to 0x00001000
Adjust rom_table_end from 0x000f0c00 to 0x00100000
Wrote linuxbios table at: 00000530 - 000006c8 checksum d93e
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3
rom_stream: 0xfff80000 - 0xfff9ffff
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
New segment addr 0x100000 size 0x3cd40 offset 0xc0 filesize 0x12d28
(cleaned up) New segment addr 0x100000 size 0x3cd40 offset 0xc0 filesize 0x12d28
New segment addr 0x13cd40 size 0x48 offset 0x12e00 filesize 0x48
(cleaned up) New segment addr 0x13cd40 size 0x48 offset 0x12e00 filesize 0x48
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000003cd40 filesz:
0x0000000000012d28
Clearing Segment: addr: 0x0000000000112d28 memsz: 0x000000000002a018
Loading Segment: addr: 0x000000000013cd40 memsz: 0x0000000000000048 filesz:
0x0000000000000048
Jumping to boot code at 0x10e514
FILO version 0.5 ([EMAIL PROTECTED]) Sun Jun 24 16:30:56 CEST 2007
menu: hda6:/boot/filo/menu.lst
hda: LBA48 250GB: ST3250824AS
Mounted ext2fs
Drive 1 does not exist
Drive 1 does not exist
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