the alix1c now boots to linux with these changes. I can login and do
all sorts of tests, ls -R, etc. I just noticed it reports the wrong
amount of memory; I have messed up an SPD setting, it seems, but let's
get this commit in and I will fix the rest over the weekend.
I still have to test some things, like ethernet; and I'd like to get
vga going, but this is a good start. Not all IO has been tested.
But USB does work, which is really great news. I plugged in a USB
media adapter and it got the interrupts and found all four devices!
mkfs etc. works fine.
I really like this board, and plan to buy some more for my own use. It
is connector-rich, which is a real plus.
ron
This set of changes adds useful debug prints.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Index: src/cpu/amd/model_lx/cpureginit.c
===================================================================
--- src/cpu/amd/model_lx/cpureginit.c (revision 2897)
+++ src/cpu/amd/model_lx/cpureginit.c (working copy)
@@ -205,7 +205,13 @@
}
}
}
+ print_debug("Try to write GLCP_DELAY_CONTROLS: hi ");
+ print_debug_hex32(msr.hi);
+ print_debug(" and lo ");
+ print_debug_hex32(msr.lo);
+ print_debug("\r\n");
wrmsr(GLCP_DELAY_CONTROLS, msr);
+ print_debug("SetDelayControl done\r\n");
return;
}
@@ -219,6 +225,7 @@
/* Castle 2.0 BTM periodic sync period. */
/* [40:37] 1 sync record per 256 bytes */
+ print_debug("Castle 2.0 BTM periodic sync period.\r\n");
msrnum = CPU_PF_CONF;
msr = rdmsr(msrnum);
msr.hi |= (0x8 << 5);
@@ -228,6 +235,7 @@
* LX performance setting.
* Enable Quack for fewer re-RAS on the MC
*/
+ print_debug("Enable Quack for fewer re-RAS on the MC\r\n");
msrnum = GLIU0_ARB;
msr = rdmsr(msrnum);
msr.hi &= ~ARB_UPPER_DACK_EN_SET;
@@ -240,22 +248,28 @@
msr.hi |= ARB_UPPER_QUACK_EN_SET;
wrmsr(msrnum, msr);
- /* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */
+ /* GLIU port active enable, limit south pole masters
+ * (AES and PCI) to one outstanding transaction.
+ */
+ print_debug(" GLIU port active enable\r\n");
msrnum = GLIU1_PORT_ACTIVE;
msr = rdmsr(msrnum);
msr.lo &= ~0x880;
wrmsr(msrnum, msr);
/* Set the Delay Control in GLCP */
+ print_debug("Set the Delay Control in GLCP\r\n");
SetDelayControl();
/* Enable RSDC */
+ print_debug("Enable RSDC\r\n");
msrnum = CPU_AC_SMM_CTL;
msr = rdmsr(msrnum);
msr.lo |= SMM_INST_EN_SET;
wrmsr(msrnum, msr);
/* FPU imprecise exceptions bit */
+ print_debug("FPU imprecise exceptions bit\r\n");
msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum);
msr.lo |= FPU_IE_SET;
@@ -263,12 +277,14 @@
/* Power Savers (Do after BIST) */
/* Enable Suspend on HLT & PAUSE instructions */
+ print_debug("Enable Suspend on HLT & PAUSE instructions\r\n");
msrnum = CPU_XC_CONFIG;
msr = rdmsr(msrnum);
msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
wrmsr(msrnum, msr);
/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
+ print_debug("Enable SUSP and allow TSC to run in Suspend\r\n");
msrnum = CPU_BC_CONF_0;
msr = rdmsr(msrnum);
msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
@@ -286,6 +302,7 @@
#endif
/* Setup throttling delays to proper mode if it is ever enabled. */
+ print_debug("Setup throttling delays to proper mode\r\n");
msrnum = GLCP_TH_OD;
msr.hi = 0;
msr.lo = 0x00000603C;
--
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