See patch. Rudolf, can you test this one to make sure it works correctly
on your board?
Thanks,
Corey
This patch removes the need to manually set up the function enable bits for the
vt8237r, by setting them up automatically depending on if the function is enabled
or not. Based on the i82801xx.
Signed-off-by: Corey Osgood <[EMAIL PROTECTED]>
Index: src/southbridge/via/vt8237r/vt8237r.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r.c (revision 2947)
+++ src/southbridge/via/vt8237r/vt8237r.c (working copy)
@@ -48,7 +48,7 @@
print_debug_hex8(where);
print_debug("failed ");
print_debug_hex8(regval);
- print_debug("\n "); /* TODO: Drop the space? */
+ print_debug("\r\n");
}
}
#else
@@ -73,13 +73,86 @@
static void vt8237r_enable(struct device *dev)
{
- struct southbridge_via_vt8237r_config *sb =
- (struct southbridge_via_vt8237r_config *)dev->chip_info;
+ u8 index = 0;
+ u16 cur_disable_mask, new_disable_mask;
+ //TODO: Use a static device for lpc_dev
+ struct device *lpc_dev = dev_find_device(0x1106, 0x3227, 0);
+
+/* List of device control functions, and their enable bits.
+ * We're going to treat rx0x50 and rx0x51 like a 16-bit register, for
+ * simplicity's sake. Device numbers are in decimal notation, not hex.
+ *
+ * bit 0: KBC
+ * bit 1: KBC Config
+ * bit 2: PS2 mouse
+ * bit 3: RTC
+ * bit 4: LAN (D18F0)
+ * bit 5: LAN clock gating
+ * bit 6: RSVD
+ * bit 7: USB Device mode (D16F5)
+ * bit 8: UHCI (D16F3)
+ * bit 9: EHCI (D16F4)
+ * bit a: UHCI (D16F2)
+ * bit b: SATA (D15F0)
+ * bit c: UHCI (D16F0)
+ * bit d: UHCI (D16F1)
+ * bit e: AC97 (D17F5)
+ * bit f: MC97 (D17F6)
+ */
+ index = PCI_FUNC(dev->path.u.pci.devfn);
+ if (PCI_SLOT(dev->path.u.pci.devfn) == 16) {
+ if (!index || index == 1)
+ index += 0xc;
+ else if (index == 2)
+ index = 0xa;
+ else if (index == 3 || index == 4)
+ index += 5;
+ else if (index == 5)
+ index = 7;
+ else return;
+ } else if (PCI_SLOT(dev->path.u.pci.devfn) == 15) {
+ /* Only D15F0 can be disabled */
+ if (!PCI_FUNC(dev->path.u.pci.devfn))
+ index = 0xb;
+ else
+ return;
+ } else if (PCI_SLOT(dev->path.u.pci.devfn) == 17) {
+ if (!index)
+ return; //southbridge
+ else
+ index += 9;
+ } else if (PCI_SLOT(dev->path.u.pci.devfn) == 18) {
+ if (!index)
+ index = 4;
+ else
+ return;
+ } else
+ return;
+
+ if (index == 0xb && !dev->enabled) {
+ u8 enables;
+
+ if (pci_read_config16(dev, 0x2) != 0x3149) return;
+ //SATA's already been disabled, now we're looking at IDE
- pci_write_config8(dev, 0x50, sb->fn_ctrl_lo);
- pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);
+ enables = pci_read_config8(dev, 0xd1);
+ enables |= (1 << 3);
+ pci_write_config8(dev, 0xd1, enables);
- /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */
+ enables = pci_read_config8(dev, 0x49);
+ enables |= (1 << 7);
+ pci_write_config8(dev, 0x49, enables);
+ }
+
+ cur_disable_mask = pci_read_config16(lpc_dev, 0x50);
+ if (dev->enabled)
+ new_disable_mask = cur_disable_mask & ~(1 << index);
+ else
+ new_disable_mask = cur_disable_mask | (1 << index);
+
+ if (new_disable_mask != cur_disable_mask)
+ pci_write_config16(lpc_dev, 0x50, new_disable_mask);
+
}
struct chip_operations southbridge_via_vt8237r_ops = {
Index: src/southbridge/via/vt8237r/chip.h
===================================================================
--- src/southbridge/via/vt8237r/chip.h (revision 2947)
+++ src/southbridge/via/vt8237r/chip.h (working copy)
@@ -25,31 +25,6 @@
extern struct chip_operations southbridge_via_vt8237r_ops;
struct southbridge_via_vt8237r_config {
- /**
- * Function disable. 1 = disabled.
- * 7 Dev 17 fn 6 MC97
- * 6 Dev 17 fn 5 AC97
- * 5 Dev 16 fn 1 USB 1.1 UHCI Ports 2-3
- * 4 Dev 16 fn 0 USB 1.1 UHCI Ports 0-1
- * 3 Dev 15 fn 0 Serial ATA
- * 2 Dev 16 fn 2 USB 1.1 UHCI Ports 4-5
- * 1 Dev 16 fn 4 USB 2.0 EHCI
- * 0 Dev 16 fn 3 USB 1.1 UHCI Ports 6-7
- */
- u16 fn_ctrl_lo;
-
- /**
- * 7 USB Device Mode 1=dis
- * 6 Reserved
- * 5 Internal LAN Controller Clock Gating 1=gated
- * 4 Internal LAN Controller 1=di
- * 3 Internal RTC 1=en
- * 2 Internal PS2 Mouse 1=en
- * 1 Internal KBC Configuration 0=dis ports 0x2e/0x2f off 0xe0-0xef
- * 0 Internal Keyboard Controller 1=en
- */
- u16 fn_ctrl_hi;
-
int ide0_enable:1;
int ide1_enable:1;
Index: src/mainboard/asus/a8v-e_se/Config.lb
===================================================================
--- src/mainboard/asus/a8v-e_se/Config.lb (revision 2947)
+++ src/mainboard/asus/a8v-e_se/Config.lb (working copy)
@@ -190,9 +190,6 @@
#both cables are 80pin
register "ide0_80pin_cable" = "1"
register "ide1_80pin_cable" = "1"
- #enables the functions of SB
- register "fn_ctrl_lo" = "0"
- register "fn_ctrl_hi" = "0xad"
device pci 0.0 on end # HT
device pci f.1 on end # IDE
--
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