Hi,
v2 and v3 have almost identical CAR setup code with identical bugs for
CAR sizes != {4k,8k,16k}. In v3, the erroneous code paths are not
triggered and the bug is latent, but we have at a few boards in v2 which
trigger these bugs, resulting in holes and/or smaller size of the CAR area.
Let's look at the v3 code:
> #ifndef CONFIG_CARSIZE
> #define CacheSize 4096
> #else
> #define CacheSize CONFIG_CARSIZE
> #endif
v2 uses DCACHE_RAM_SIZE instead of CONFIG_CARSIZE
[...]
> clear_fixed_var_mtrr_out:
>
> #if CacheSize == 0x10000
> /* enable caching for 64K using fixed mtrr */
> movl $0x268, %ecx /* fix4k_c0000*/
> movl $0x06060606, %eax /* WB IO type */
> movl %eax, %edx
> wrmsr
> movl $0x269, %ecx
> wrmsr
> #endif
OK, 64k are working.
> #if CacheSize == 0x8000
> /* enable caching for 32K using fixed mtrr */
> movl $0x269, %ecx /* fix4k_c8000*/
> movl $0x06060606, %eax /* WB IO type */
> movl %eax, %edx
> wrmsr
> #endif
OK, 32k are working.
> /* enable caching for 16K/8K/4K using fixed mtrr */
> movl $0x269, %ecx /* fix4k_cc000*/
> #if CacheSize == 0x4000
> movl $0x06060606, %edx /* WB IO type */
> #endif
> #if CacheSize == 0x2000
> movl $0x06060000, %edx /* WB IO type */
> #endif
> #if CacheSize == 0x1000
> movl $0x06000000, %edx /* WB IO type */
> #endif
> xorl %eax, %eax
> wrmsr
Disable CAR between 16k and 32k unconditionally. Even if CacheSize is
32k or 64k. Not nice. This affects the following boards:
./src/mainboard/amd/db800/Options.lb:default DCACHE_RAM_SIZE=0x08000
./src/mainboard/amd/norwich/Options.lb:default DCACHE_RAM_SIZE=0x08000
./src/mainboard/amd/serengeti_cheetah/Options.lb:default
DCACHE_RAM_SIZE=0x08000
./src/mainboard/msi/ms7260/Options.lb:default DCACHE_RAM_SIZE = 0x08000
./src/mainboard/asus/a8n_e/Options.lb:default DCACHE_RAM_SIZE=0x08000
./src/mainboard/tyan/s2912/Options.lb:default DCACHE_RAM_SIZE=0x08000
./src/mainboard/artecgroup/dbe61/Options.lb:default DCACHE_RAM_SIZE=0x08000
./src/mainboard/supermicro/h8dmr/Options.lb:default DCACHE_RAM_SIZE=0x08000
./src/mainboard/pcengines/alix1c/Options.lb:default DCACHE_RAM_SIZE=0x08000
./src/mainboard/nvidia/l1_2pvv/Options.lb:default DCACHE_RAM_SIZE=0x08000
./src/mainboard/digitallogic/msm800sev/Options.lb:default
DCACHE_RAM_SIZE=0x08000
./src/mainboard/gigabyte/ga_2761gxdk/Options.lb:default
DCACHE_RAM_SIZE=0x08000
./src/mainboard/gigabyte/m57sli/Options.lb:default DCACHE_RAM_SIZE=0x08000
If CacheSize is not one of 4k,8k,16k,32k,64k, we will not set up CAR at
all. This affects the following board:
./src/mainboard/iwill/dk8_htx/Options.lb:default DCACHE_RAM_SIZE=0x0c000
---------------------------------------------------------------------------------------------
Clean up handling different CAR sizes and round down CAR size to the
nearest power of two.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
---
Index: LinuxBIOSv3-CAR/arch/x86/stage0_i586.S
===================================================================
--- LinuxBIOSv3-CAR/arch/x86/stage0_i586.S (Revision 510)
+++ LinuxBIOSv3-CAR/arch/x86/stage0_i586.S (Arbeitskopie)
@@ -301,37 +301,36 @@
jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out:
-#if CacheSize == 0x10000
- /* enable caching for 64K using fixed mtrr */
- movl $0x268, %ecx /* fix4k_c0000*/
- movl $0x06060606, %eax /* WB IO type */
- movl %eax, %edx
- wrmsr
- movl $0x269, %ecx
- wrmsr
-#endif
+ /* We round down CAR size to the next power of 2 */
+ movl $0x269, %ecx /* fix4k_c8000*/
-#if CacheSize == 0x8000
+#if CacheSize >= 0x8000
/* enable caching for 32K using fixed mtrr */
- movl $0x269, %ecx /* fix4k_c8000*/
movl $0x06060606, %eax /* WB IO type */
movl %eax, %edx
wrmsr
#endif
+#if CacheSize => 0x10000
+ /* enable caching for 32K-64K using fixed mtrr */
+ movl $0x268, %ecx /* fix4k_c0000*/
+ wrmsr
+#endif
+
+#if CacheSize < 0x10000
/* enable caching for 16K/8K/4K using fixed mtrr */
- movl $0x269, %ecx /* fix4k_cc000*/
-#if CacheSize == 0x4000
+#if CacheSize >= 0x4000
movl $0x06060606, %edx /* WB IO type */
-#endif
-#if CacheSize == 0x2000
+#elif CacheSize >= 0x2000
movl $0x06060000, %edx /* WB IO type */
-#endif
-#if CacheSize == 0x1000
+#elif CacheSize >= 0x1000
movl $0x06000000, %edx /* WB IO type */
+#else
+#error Invalid CAR size, must be at least 4k.
#endif
xorl %eax, %eax
wrmsr
+#endif
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* enable write base caching so we can do execute in place
--
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