On Dec 27, 2007 1:22 PM, ron minnich <[EMAIL PROTECTED]> wrote: > yes I think you are probably right but how are the fixed mtrr's set? > > I don't know, This still seems like memory timing issues to me but who > knows. > > ron >
ron, you're right, it's a dram configuration problem. after I set the dram clocking control and signal timing control registers, it worked well after enabling memory cache. Hmm...these registers have nothing to do when cache disabled? and they are not mentioned in the bios porting guide either
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