This is so we can attempt to return from disable_car: we need these definitions in C. Besides, they make more sense in a .h I think.
ron
Move defines from a .S to a .h so they are available to C. Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]> Index: include/arch/x86/amd_geodelx.h =================================================================== --- include/arch/x86/amd_geodelx.h (revision 542) +++ include/arch/x86/amd_geodelx.h (working copy) @@ -567,7 +567,24 @@ /* ------------------------ */ #define DCACHE_RAM_SIZE 0x08000 #define DCACHE_RAM_BASE 0xc8000 +/* This is where the DCache will be mapped and be used as stack. It would be + * cool if it was the same base as LinuxBIOS normal stack. + */ +#define LX_STACK_BASE DCACHE_RAM_BASE +#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) +#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ +#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ +#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) +#define CR0_CD 0x40000000 /* Bit 30 = Cache Disable */ +#define CR0_NW 0x20000000 /* Bit 29 = Not Write Through */ + +#define ROM_CODE_SEG 0x08 +#define ROM_DATA_SEG 0x10 + +#define CACHE_RAM_CODE_SEG 0x18 +#define CACHE_RAM_DATA_SEG 0x20 + /* POST CODES */ /* standard AMD post definitions -- might as well use them. */ Index: arch/x86/geodelx/stage0.S =================================================================== --- arch/x86/geodelx/stage0.S (revision 542) +++ arch/x86/geodelx/stage0.S (working copy) @@ -28,24 +28,6 @@ #include "../macros.h" #include <amd_geodelx.h> -/* This is where the DCache will be mapped and be used as stack. It would be - * cool if it was the same base as LinuxBIOS normal stack. - */ -#define LX_STACK_BASE DCACHE_RAM_BASE -#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) - -#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ -#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ -#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) -#define CR0_CD 0x40000000 /* Bit 30 = Cache Disable */ -#define CR0_NW 0x20000000 /* Bit 29 = Not Write Through */ - -#define ROM_CODE_SEG 0x08 -#define ROM_DATA_SEG 0x10 - -#define CACHE_RAM_CODE_SEG 0x18 -#define CACHE_RAM_DATA_SEG 0x20 - .code16 .globl _stage0 _stage0:
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