Author: hailfinger
Date: 2008-01-05 00:19:49 +0100 (Sat, 05 Jan 2008)
New Revision: 546
Modified:
LinuxBIOSv3/arch/x86/geodelx/stage1.c
LinuxBIOSv3/include/arch/x86/amd_geodelx.h
Log:
These changes implement a fixed Geode LX Cache As Ram that allows a
return from disable_car.
- Move the cache as ram memory to 0x80000 instead of 0xc8000, as the C
range is really tricky to get right :-)
- Modify the geode disable_car to ensure the cache is flushed to ram on
the wbinvd.
With these changes, I get a payload loaded.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/stage1.c 2008-01-04 23:14:10 UTC (rev
545)
+++ LinuxBIOSv3/arch/x86/geodelx/stage1.c 2008-01-04 23:19:49 UTC (rev
546)
@@ -22,6 +22,7 @@
#include <lib.h>
#include <msr.h>
#include <amd_geodelx.h>
+#include <console.h>
static const struct msrinit msr_table[] = {
/* Setup access to cache under 1MB. */
@@ -59,5 +60,12 @@
for (i = 0; i < ARRAY_SIZE(msr_table); i++)
wrmsr(msr_table[i].msrnum, msr_table[i].msr);
- __asm__("wbinvd\n");
+ /* OK, here is the theory: we should be able to copy
+ * the data back over itself, and the wbinvd should then
+ * flush to memory. Let's see.
+ */
+ __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S"
(DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
+ __asm__ __volatile__ ("wbinvd\n");
+ banner(BIOS_DEBUG, "Disable_car: done wbinvd");
+ banner(BIOS_DEBUG, "disable_car: done");
}
Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:14:10 UTC (rev
545)
+++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:19:49 UTC (rev
546)
@@ -566,12 +566,17 @@
/* ------------------------ */
#define DCACHE_RAM_SIZE 0x08000
-#define DCACHE_RAM_BASE 0xc8000
+#define DCACHE_RAM_BASE 0x80000
/* This is where the DCache will be mapped and be used as stack. It would be
* cool if it was the same base as LinuxBIOS normal stack.
*/
#define LX_STACK_BASE DCACHE_RAM_BASE
#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4)
+/* This is where the DCache will be mapped and be used as stack. It would be
+ * cool if it was the same base as LinuxBIOS normal stack.
+ */
+#define LX_STACK_BASE DCACHE_RAM_BASE
+#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4)
#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */
#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */
--
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