-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello,
Attached patch documents the GPIO setup of the board (check board wiki page) and fixes the W83627EHF settings for suspend. Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]> Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFHgB3n3J9wPJqZRNURAqEWAJ9xjgUJLuOu4+71eUIx+XR37lPyRQCgyy/o /GF966Lx1IMR4yLm+p3Y9rA= =YGr3 -----END PGP SIGNATURE-----
Index: src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c =================================================================== --- src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c (revision 2978) +++ src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c (working copy) @@ -79,6 +79,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC) static void memreset_setup(void) @@ -174,18 +175,31 @@ pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + reg = pnp_read_config(ACPI_DEV, 0xe6); + /* Set the delay rising time from PWROK_LP to PWROK_ST to 300 - 600ms, and 0 to vice versa */ + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + pnp_enter_ext_func_mode(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); - pnp_write_config(GPIO_DEV, 0xe0, 0xde); // 1101110 0=output 1=input - pnp_write_config(GPIO_DEV, 0xe1, 0x1); //set output val - pnp_write_config(GPIO_DEV, 0xe2, 0x0); //no inversion - pnp_write_config(GPIO_DEV, 0xe3, 0x3); //0000 0011 0=output 1=input - pnp_write_config(GPIO_DEV, 0xe4, 0xa4); //set output val - pnp_write_config(GPIO_DEV, 0xe5, 0x0); //no inversion - pnp_write_config(GPIO_DEV, 0x30, 0x9); //Enable GPIO 2 & GPIO 5 pnp_exit_ext_func_mode(GPIO_DEV); + /* set memory voltage to 2.75V chipset voltage, vcore offset + 100mV, 1.5V Chipset voltage */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101110 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x1); /* set output val */ + pnp_write_config(GPIO_DEV, 0xe2, 0x0); /* no inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x3); /* 0000 0011 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe4, 0xa4); /* set output val 1010 0100 */ + pnp_write_config(GPIO_DEV, 0xe5, 0x0); /* no inversion */ + pnp_write_config(GPIO_DEV, 0x30, 0x9); /* Enable GPIO 2 & GPIO 5 */ + pnp_exit_ext_func_mode(GPIO_DEV); + w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); @@ -272,17 +286,26 @@ pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + reg = pnp_read_config(ACPI_DEV, 0xe6); + /* Set the delay rising time from PWROK_LP to PWROK_ST to 300 - 600ms, and 0 to vice versa */ + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + pnp_enter_ext_func_mode(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); - pnp_write_config(GPIO_DEV, 0xe0, 0xde); // 1101110 0=output 1=input - pnp_write_config(GPIO_DEV, 0xe1, 0x1); //set output val - pnp_write_config(GPIO_DEV, 0xe2, 0x0); //no inversion - pnp_write_config(GPIO_DEV, 0xe3, 0x3); //0000 0011 0=output 1=input - pnp_write_config(GPIO_DEV, 0xe4, 0xa4); //set output val - //0x10 seems to control something with SGD VIA - - pnp_write_config(GPIO_DEV, 0xe5, 0x0); //no inversion - pnp_write_config(GPIO_DEV, 0x30, 0x9); //Enable GPIO 2 & GPIO 5 + /* set memory voltage to 2.75V chipset voltage, vcore offset + 100mV, 1.5V Chipset voltage */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101110 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x1); /* set output val */ + pnp_write_config(GPIO_DEV, 0xe2, 0x0); /* no inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x3); /* 0000 0011 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe4, 0xa4); /* set output val 1010 0100 */ + pnp_write_config(GPIO_DEV, 0xe5, 0x0); /* no inversion */ + pnp_write_config(GPIO_DEV, 0x30, 0x9); /* Enable GPIO 2 & GPIO 5 */ pnp_exit_ext_func_mode(GPIO_DEV);
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