On Tue, 6 Feb 2001, Richard A. Smith wrote:
> I am hopeing that one of you Gurus can tell me how the hell the A20
> line is supposed to work on the hardware level. We finally got our
> first prototype board (mostly) populated and have begun the process of
> bringing up the design. For reminders its a 400 Mhz Celeron using the
> 440bx chipset.
A20 is a legacy of the original PC. Here is a nice writeup:
http://www.smsc.com/main/appnotes/an612.html
Now, I actually used to design microprocessor boards for a living. I was
pretty good at it, and I did an 8086 board once, and it was a good
design. It was good because I took all the Intel design notes and trashed
them, and ignored the Intel IO chips, and designed my own. It's
interesting that my least-favorite IO chips on the motherboards we have
are all ... Intel.
Which is why I have so much trouble with the PC architecture. If you look
at the original PC, it looks like someone Xeroxed(TM) the Intel design
notes and built a card. It's quite ugly. The PC hardware is such a BAD
design, and we continually fight its defects to this day.
Such as A20.
What happened: The original 8086 was a 20-bit address machine. So you got
A19:A0 for address. But, on this machine, you could define a
segment:offset pair which wrapped past address 0 (e.g. 0xfff0:0xffff).
"Clever" programmers evidently used this feature (we can hope they've all
gone to other types of work).
Enter the 80286. Guess what: wrap to 0 no longer works. What to do? Well,
you need a signal to "Gate A20" so that you can enable or disable it. When
Gate A20 is asserted, address line A20 can NOT be asserted -- the A20 line
is gated. Stupid 8086 code that wants to wrap will then work.
How is Gate A20 controlled? In the classic design (IBM?) FROM THE
KEYBOARD. Elegant, yes? I mean, why would you not control processor
address lines from a keyboard?
I hope this helps for the meaning of gate a20. I've ignored this horrible
thing until today. It makes my brain ache.
> Our first hurdle was that the Southbridge was ignoreing the reset
> vector. Walking all the lines showed that all was well the processor
> was issueing (0xFFFF0). Eventually we went ahead and looked at the
> rest of the lines and found that they were all high as well except for
> the A20 line which we thought was normal.
My guess then is that A20 was being masked. What was the value of the A20
Mask line before you cut it? If it was 0, then A20 was being gated, I
guess.
> We double checked that we had it hooked up just like the Intel ref design.
Well, those ref designs are always just that -- ref. Any errors are your
trouble.
> 1) Just what exactly does all the A20 mask stuff do anyway?
see above
> 2) Why does the southbridge only respond to addresses in the
> 0xFFFFxxxx for BIOS when the data sheets seem to indicate that both
> ranges should be decoded.
I don't know BUT: do you care? You don't really need those low-order
addresses for linuxbios. So if you have a mode that works, I would use
that.
Also, are you sure that it is not responding to ffff0? I don't think
you've issued that address, just fffff000
ron
