[EMAIL PROTECTED] (Eric W. Biederman) writes:
> In:
> Intel_Architecture_Software_Developers_Manual,_Volume_3:_System_Programming.pdf
>
> aka
> 24319202.pdf
>
> on page: (335) aka 9-11
>
> It describes caching behavior when CD & NW are set but there are valid
> cache blocks in the cache. Basically it says in such a situation no cache
> blocks
>
> are played with but the existing cache blocks are used.
>
> So with the proper prefill algorithm doing the memory init from C code
> should be possible. My problem: filling the Level-1 Data cache is
> simple (so C doing memory init in C will happen). Filling the Level-1
> Instruction cache, is this possible without executing the
> instructions?
O.k. I have built a proof of concept implementation. And replaced
all of the CALLSP & CALL_LABEL calls in the current memory
initialization with plain call & ret calls, and it worked!. So I will
start moving the memory initialization to C.
I still do not know how to prefill the L1 I-cache ideas?
This should allow creating a fairly generic IPL.S for the Doc
millenium for an arbitrary board, and a PIII processor. ROM write
enable looks like the only board level variable you would need to
introduce. The cache initialization of the PII looks to nasty to fit
in 512 bytes. Heck it looks to nasty to move out of C.
O.k. Tommorrow I will get back to my elf boot interface code,
documenting it and writing the code for linuxBIOS on x86 and alpha.
Eric
