Ollie Lho <[EMAIL PROTECTED]> writes:
> Ron,
> I just committed a bunch of code for SiS 550 SoC support. I made a
> lot of changes to solve Pentium v.s. Pentium Pro incompability. The
> current
> code in CVS should works fine for both SiS 630+Celeron and SiS 550.
> Please
> check it out to see if I had made any mistake.
>
> There is a new #ifdef IOPAIC stuff in hardwaremain.c which
> I have no idea how to do it correctly.
I how that is IO_APIC...
Anyway except for the L440GX I don't think any of the board we have
been using actually has one. The fact that initializing a non-existent
IOAPIC has been working has been absolute fascinating...
Making it conditional sounds like the right move. I'll check it over
in the coming weeks as I bring up the dual AMD board. Since I have an
L440GX as well I should be able to test both paths through the code.
Ollie could you give me a hint as to which register needs to get set
on the Athlons to enable L2 cache. I have made a first pass through
my docs from AMD (obtained under NDA grumble grumble) and I haven't
seen anything. At least for the current generation of processors.
Eric
