This is an anonymous contribution, I don't remember if I sent it already.
Interesting stuff.
ron
---------- Forwarded message ----------
Date: Thu, 30 Nov 2000 10:18:31 -0800 (PST)
To: [EMAIL PROTECTED]
Subject: ServerWorks DRAM stuff...
Here are some descriptions of registers on the
ServerWorks CNB30LE NorthBridge for configuring
and initializing the DRAM. Consider it an
anonymous donation...
:)
-- Memory Upper Limit Register: 70h
PA<31:24> = (MB << 20), eg:
64M: 04h
128M: 08h
256M: 10h
512M: 20h
-- Refresh Counter Register: 79h
16h for 100MHz SDRAM,
1Eh for 133MHz SDRAM
-- SDRAM Power On Sequence Register: 7Bh
init sequence:
1. program all memory registers
2. set bit 2
3. delay 100+ usec
4. set bit 3
5. delay 200+ usec
6. set bit 0
7. wait 16+ refresh cycles
8. set bit 1
9. enable memory controller (bit 0 of reg 92h)
bit 4: stop refresh when set.
load RCR register and start
counting when cleared
bit 3: stop SDRAM NOP command
bit 2: start SDRAM NOP command
bit 1: write SDRAM Mode Register command
bit 0: precharge the SDRAM
-- Row Attribute Registers
RAR0: 7Ch (rows 0 & 1)
RAR1: 7Dh (rows 2 & 3)
RAR2: 7Eh (rows 4 & 5)
RAR3: 7Fh (rows 6 & 7)
bits 7-4: SDRAM organization in ROW 1
(index from table)
bits 3-0: SDRAM organization in ROW 0
(index from table)
0: 64M 4-bank 12x8
1: 16M 2-bank 11x9
2: 16M 2-bank 11x10
3: 128M 4-bank 12x11
4: 256M 4-bank 13x11
5: 64M 2-bank 13x10
6: 64M 4-bank 12x10
7: 64M 4-bank 12x9
8: 256M 4-bank 13x10
9: 256M 4-bank 13x9
a: 256M 4-bank 13x8
b: 256M 4-bank 12x9
c: 256M 4-bank 12x10
-- Memory Row Decode Registers
lower and upper bound addresses for each row (16MB
aligned)
0: L=80h, U=81h
1: L=82h, U=82h
...
7: L=8Eh, U=8Fh
-- Memory Row Presence Register: 90h
each bit corresponds to a memory row,
and is set if present
-- Memory Timing Control Register: 91h
bit 7: tRAS (0=6 Clks, 1=5 Clks)
bit 6: tRCD (0=3 Clks, 1=2 Clks)
bit 5: tRP (0=3 Clks, 1=2 Clks)
bit 4-3: tRC (00b=10, 01b=9, 10b=8, 11b=7 Clks)
bit 2: tRWL (0=2 Clks, 1=1 Clks)
bit 1: memory overlapping.
NOT set if tRP=2 or tRCD=2 or CAS=2
-- Bridge Configuration Register 2: 92h
bit 3: enhanced page hit timing, 0=10-1-1-1, 1=9-1-1-1
bit 1: SDRAM CAS Latency (0=CAS 3, 1=CAS 2)
bit 0: memory controller enable
-- Auxillary Options Register: FDh
bit 4: chip select signal buffer select (set to 1)
bit 3: memory address buffer select for copy A
bit 1: memory address buffer select for copy B
bit 0: memory data buffer select
(set bits 0,1,3 to 1 if >2 rows are populated)
