I'm CC'ing this to the linuxBIOS list because it is on topic there. Ollie Lho <[EMAIL PROTECTED]> writes: > "Eric W. Biederman" wrote: > > > > If the chip is out on the ISA bus unless you set up approriate > > decoders for it, the chip PCI->ISA bridge will be doing subtractive > > decode which will slow you down. > > > > Eric, > What is "subtractive decode" and why it makes things slow ?? O.k. Quick PCI lesson. When a PCI request is put on the bus. A fast PCI devices will answer the next bus cycle. A medium PCI device will answer 2 cycles after the request. A PCI device setup for subtractive decode will answer 3 or is it 4 PCI cycles after the request. A PCI->ISA bridge is usually configured for subtractive decode and will answer not just the PCI request it is configured to in it's BAR registers but all PCI requests that might possibly be for ISA devices. So you can make a hybrid PCI/ISA devices like the i82559 interrupt controller built into most southbridges respond faster by configuring a PCI bar register to decode the cycle in fast or medium mode. The combination of slow device response plus small transfer sizes gives slow transfers for ISA devices. Use DMA when you can to ISA devices, it's not the reduction in cpu overhead but the more efficient use of the PCI bus that makes it fast. There is of course the ISA overhead, and that might further slow the transfer over the PCI bus. In the JFFS case that initially triggered this question it may have been the flash device was a slow device on the ISA bus. However the initial investigation revealed that there was enough overhead in JFFS a flash device read was getting 4X or so better transfer rates than JFFS was getting. So I didn't pursue this to see if these numbers were all theoretical or not. Eric
