Marty Connor <[EMAIL PROTECTED]> writes:
> I'll be interested to know what sort of machine and motherboard I should
> get to do an effective demo. I don't know if you already got the 3Com
> Etherboot driver you needed, but let me know and I'll see what I can do.
> If I can find a card, I can probably do something useful.
I now have my onboard 3 com nic working. If only I'd realized I had
to put the new PCI id into config.c I would have had this working
much earlier.
Starting with the eepro100 was lucky it contained the necessary code
to enable a pci device. That is setting up the command word so the
pci device will function as a bus master, and setting the latency timer.
Anyway after adding the pci id into config.c as well as NIC, and
adding the pci initialization code to the 3c90x driver my onboard 3COM
nic is now working fine.
I have also fixed a few minor bugs in the eepro100 driver pertaining
to this. I suspect the pci enable code should probably be moved into
a common function so that all of the etherboot drivers pci can share
it. Any of them that need to run under linuxBIOS will need this at
least, and it can't hurt with a normal BIOS.
Eric
diff -uNr --exclude=Roms etherboot-5.1.0.eb1/src/3c90x.c
etherboot-5.1.0.eb2/src/3c90x.c
--- etherboot-5.1.0.eb1/src/3c90x.c Fri Apr 6 12:31:54 2001
+++ etherboot-5.1.0.eb2/src/3c90x.c Thu Jun 21 23:15:56 2001
@@ -685,8 +685,26 @@
unsigned int mopt;
unsigned short linktype;
+ unsigned short pci_command;
+ unsigned short new_command;
+ unsigned char pci_latency;
+
if (probeaddrs == 0 || probeaddrs[0] == 0)
return 0;
+
+ /* Make certain the card is properly set up as a bus master. */
+ pcibios_read_config_word(pci->bus, pci->devfn, PCI_COMMAND, &pci_command);
+ new_command = pci_command | PCI_COMMAND_MASTER | PCI_COMMAND_MEM | PCI_COMMAND_IO;
+ if (pci_command != new_command) {
+ printf("\nThe PCI BIOS has not enabled this device!\nUpdating PCI command
+%x->%x. pci_bus %x pci_device_fn %x\n",
+ pci_command, new_command, pci->bus, pci->devfn);
+ pcibios_write_config_word(pci->bus, pci->devfn, PCI_COMMAND, new_command);
+ }
+ pcibios_read_config_byte(pci->bus, pci->devfn, PCI_LATENCY_TIMER, &pci_latency);
+ if (pci_latency < 32) {
+ printf("\nPCI latency timer (CFLT) is unreasonably low at %d. Setting to
+32 clocks.\n", pci_latency);
+ pcibios_write_config_byte(pci->bus, pci->devfn, PCI_LATENCY_TIMER, 32);
+ }
INF_3C90X.IOAddr = probeaddrs[0] & ~3;
INF_3C90X.CurrentWindow = 255;
diff -uNr --exclude=Roms etherboot-5.1.0.eb1/src/NIC etherboot-5.1.0.eb2/src/NIC
--- etherboot-5.1.0.eb1/src/NIC Thu Jun 21 22:54:32 2001
+++ etherboot-5.1.0.eb2/src/NIC Thu Jun 21 22:57:19 2001
@@ -69,6 +69,7 @@
3c905b-t4 3c90x 0x10b7,0x9056
3c905b-fx 3c90x 0x10b7,0x905a
3c905c-tpo 3c90x 0x10b7,0x9200
+3c980 3c90x 0x10b7,0x9800
# Intel Etherexpress Pro/100
eepro100 eepro100 0x8086,0x1229
82559er eepro100 0x8086,0x1209
diff -uNr --exclude=Roms etherboot-5.1.0.eb1/src/config.c
etherboot-5.1.0.eb2/src/config.c
--- etherboot-5.1.0.eb1/src/config.c Thu Jun 21 22:55:20 2001
+++ etherboot-5.1.0.eb2/src/config.c Thu Jun 21 22:55:22 2001
@@ -54,6 +54,8 @@
"3Com905B-FL", 0, 0, 0, 0},
{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C_TXM,
"3Com905C-TXM", 0, 0, 0, 0},
+ { PCI_VENDOR_ID_3COM, 0x9800,
+ "3Com980-Cyclone", 0, 0, 0, 0},
#endif
#ifdef INCLUDE_3C595
{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C590,
@@ -76,6 +78,8 @@
"3Com900B-2/T", 0, 0, 0, 0},
{ PCI_VENDOR_ID_3COM, 0x900A,
"3Com900B-FL", 0, 0, 0, 0},
+ { PCI_VENDOR_ID_3COM, 0x9800,
+ "3Com980-Cyclone", 0, 0, 0, 0},
#endif
#ifdef INCLUDE_EEPRO100
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557,
diff -uNr --exclude=Roms etherboot-5.1.0.eb1/src/eepro100.c
etherboot-5.1.0.eb2/src/eepro100.c
--- etherboot-5.1.0.eb1/src/eepro100.c Sat Apr 21 05:34:25 2001
+++ etherboot-5.1.0.eb2/src/eepro100.c Thu Jun 21 23:15:03 2001
@@ -487,7 +487,6 @@
int options;
int promisc;
- unsigned char pci_bus = 0;
unsigned short pci_command;
unsigned short new_command;
unsigned char pci_latency;
@@ -508,19 +507,19 @@
* from eepro100.c in 2.2.9 kernel source
*/
- pcibios_read_config_word(pci_bus, p->devfn, PCI_COMMAND, &pci_command);
+ pcibios_read_config_word(p->bus, p->devfn, PCI_COMMAND, &pci_command);
new_command = pci_command | PCI_COMMAND_MASTER|PCI_COMMAND_IO;
if (pci_command != new_command) {
printf("\nThe PCI BIOS has not enabled this device!\nUpdating
PCI command %x->%x. pci_bus %x pci_device_fn %x\n",
- pci_command, new_command, pci_bus, p->devfn);
- pcibios_write_config_word(pci_bus, p->devfn, PCI_COMMAND,
new_command);
+ pci_command, new_command, p->bus, p->devfn);
+ pcibios_write_config_word(p->bus, p->devfn, PCI_COMMAND,
+new_command);
}
- pcibios_read_config_byte(pci_bus, p->devfn, PCI_LATENCY_TIMER,
&pci_latency);
+ pcibios_read_config_byte(p->bus, p->devfn, PCI_LATENCY_TIMER,
+&pci_latency);
if (pci_latency < 32) {
printf("\nPCI latency timer (CFLT) is unreasonably low at %d.
Setting to 32 clocks.\n", pci_latency);
- pcibios_write_config_byte(pci_bus, p->devfn,
PCI_LATENCY_TIMER, 32);
+ pcibios_write_config_byte(p->bus, p->devfn, PCI_LATENCY_TIMER,
+32);
}
}
diff -uNr --exclude=Roms etherboot-5.1.0.eb1/src/pci.h etherboot-5.1.0.eb2/src/pci.h
--- etherboot-5.1.0.eb1/src/pci.h Wed Apr 18 09:22:51 2001
+++ etherboot-5.1.0.eb2/src/pci.h Thu Jun 21 23:30:22 2001
@@ -22,6 +22,7 @@
*/
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
+#define PCI_COMMAND_MEM 0x2 /* Enable response in mem
+space */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
