RE: Current state of 815ep port..

hcyun Wed, 31 Oct 2001 15:47:35 -0800

Title: Current state of 815ep port..

woops.. bottom lines of this mail are removed..

I attach the whole log message.

Below is output when i skip ramtest.
------------------------------
Ram1
Ram2
50:44                   // (register number : value) pairs that i setted.
50:44
72:00002028
53:18
92:00003eae
94:0000fffe
99:80
9a:00
9b:80
Ram3
Ram Enable 1
Ram Enable 2
Ram Enable 3
Ram Enable 4
Ram Enable 5
Ram4
Ram5
Ram6
LinuxBIOS booting...
Finding PCI configuration type.
PCI: Using configuration type 1
Scanning PCI bus...PCI: pci_scan_bus for bus 0
PCI: 00:00 [8086/1130]
PCI: 00:08 [8086/1131]
PCI: 00:f0 [8086/244e]
PCI: 00:f8 [8086/2440]
PCI: 00:f9 [8086/244b]
PCI: 00:fa [8086/2442]
PCI: 00:fb [8086/2443]
PCI: 00:fc [8086/2444]
PCI: 00:fd [8086/2445]
PCI: 00:fe [8086/2446]
PCI: pci_scan_bus for bus 1
PCI: 01:00 [10de/0110]
PCI: pci_scan_bus returning with max=01
PCI: pci_scan_bus for bus 2
PCI: 02:08 [8086/1229]
PCI: 02:10 [104c/ac50]
PCI: 02:28 [104c/8020]
PCI: 02:50 [1274/5880]
PCI: pci_scan_bus returning with max=02
PCI: pci_scan_bus returning with max=02
done
DRP0 = 0xe
DIMM0 - size = 256M
DIMM1 - size = 0M
DRP1 = 0x0
DIMM2 - size = 0M
totalram: 256M
Initializing CPU #0
Updating microcode
microcode_info: sig = 0x00000686 pf=0x00000010 rev = 0x00000000
Enabling cache...
Setting variable MTRR 0, base:    0MB, range: 256MB, type: WB
Setting variable MTRR 1, base: 256MB, range:    0MB, type: UC
done.

Max cpuid index    : 3
Vendor ID          : GenuineIntel
Processor Type     : 0x00
Processor Family   : 0x06
Processor Model    : 0x08
Processor Mask     : 0x00
Processor Stepping : 0x06
Feature flags      : 0x0387fbff

Cache/TLB descriptor values: 1 reads required
Desc 0x01 : Instr TLB: 4KB pages, 4-way set assoc, 32 entries
Desc 0x02 : Instr TLB: 4MB pages, fully assoc, 2 entries
Desc 0x03 : Data TLB: 4KB pages, 4-way set assoc, 64 entries
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x82 : L2 Unified cache: 256K bytes, 8-way set assoc, 32 byte line size
Desc 0x08 : Inst cache: 16K bytes, 4-way set assoc, 32 byte line size
Desc 0x04 : Data TLB: 4MB pages, 4-way set assoc, 8 entries
Desc 0x0c : Data cache: 16K bytes, 2-way or 4-way set assoc, 32 byte line size

op: 0x03 eax:0x00000000 ebx:0x00000000 ecx:0x4027736e edx:0x0002ce88

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Configuring L2 cache...CPU signature of 680 so no L2 cache configuration
Enable Cache
done.
Disabling local apic...done.
CPU #0 Initialized
Allocating PCI resources...COMPUTE_ALLOCATE: do IO
compute_allocate_io: base 0x1000
compute_allocate_io: base 0x1000
DEVIO: Bus 0x2, devfn 0x8, reg 0x1: iosize 0x20
-->set base to 0x1000
DEVIO: Bus 0x2, devfn 0x50, reg 0x0: iosize 0x40
-->set base to 0x1020
BUS 2: set iolimit to 0x1fff
BUSIO: done Bridge Bus 0x2, iobase now 0x2000
compute_allocate_io: base 0x2000
BUS 1: set iolimit to 0x1fff
BUSIO: done Bridge Bus 0x1, iobase now 0x2000
DEVIO: Bus 0x0, devfn 0xf9, reg 0x4: iosize 0x10
-->set base to 0x2000
DEVIO: Bus 0x0, devfn 0xfa, reg 0x4: iosize 0x20
-->set base to 0x2010
DEVIO: Bus 0x0, devfn 0xfb, reg 0x4: iosize 0x10
-->set base to 0x2030
DEVIO: Bus 0x0, devfn 0xfc, reg 0x4: iosize 0x20
-->set base to 0x2040
DEVIO: Bus 0x0, devfn 0xfd, reg 0x0: iosize 0x100
-->set base to 0x2060
DEVIO: Bus 0x0, devfn 0xfd, reg 0x1: iosize 0x40
-->set base to 0x2160
DEVIO: Bus 0x0, devfn 0xfe, reg 0x0: iosize 0x100
-->set base to 0x21a0
DEVIO: Bus 0x0, devfn 0xfe, reg 0x1: iosize 0x80
-->set base to 0x22a0
BUS 0: set iolimit to 0x2fff
COMPUTE_ALLOCATE: do MEM
compute_allocate_mem: base 0x80000000
compute_allocate_mem: base 0x80000000
DEVMEM: Bus 0x2, devfn 0x8, reg 0x2: memsize 0x100000
-->set base to 0x80000000
DEVMEM: Bus 0x2, devfn 0x10, reg 0x0: memsize 0x1000
-->set base to 0x80100000


Ram1
Ram2
50:44
50:44
72:00000000
72:00002028
53:00
53:18
92:0000ffff
92:00003eae
94:0000ffff
94:0000fffe
98:66
99:00
9a:66
9b:00
98:00
99:80
9a:00
9b:80
Ram3
Ram Enable 1
Ram Enable 2
Ram Enable 3
Ram Enable 4
Ram Enable 5
Ram4
Ram5
Ram6
LinuxBIOS booting...
Finding PCI configuration type.
PCI: Using configuration type 1
Scanning PCI bus...PCI: pci_scan_bus for bus 0
PCI: 00:00 [8086/1130]
PCI: 00:08 [8086/1131]
PCI: 00:f0 [8086/244e]
PCI: 00:f8 [8086/2440]
PCI: 00:f9 [8086/244b]
PCI: 00:fa [8086/2442]
PCI: 00:fb [8086/2443]
PCI: 00:fc [8086/2444]
PCI: 00:fd [8086/2445]
PCI: 00:fe [8086/2446]
PCI: pci_scan_bus for bus 1
PCI: 01:00 [10de/0110]
PCI: pci_scan_bus returning with max=01
PCI: pci_scan_bus for bus 2
PCI: 02:08 [8086/1229]
PCI: 02:10 [104c/ac50]
PCI: 02:28 [104c/8020]
PCI: 02:50 [1274/5880]
PCI: pci_scan_bus returning with max=02
PCI: pci_scan_bus returning with max=02
done
DRP0 = 0xe
DIMM0 - size = 256M
DIMM1 - size = 0M
DRP1 = 0x0
DIMM2 - size = 0M
totalram: 256M
Initializing CPU #0
Updating microcode
microcode_info: sig = 0x00000686 pf=0x00000010 rev = 0x00000000
Enabling cache...
Setting variable MTRR 0, base:    0MB, range:  256MB, type: WB
Setting variable MTRR 1, base:  256MB, range:    0MB, type: UC
done.


Max cpuid index    : 3
Vendor ID          : GenuineIntel
Processor Type     : 0x00
Processor Family   : 0x06
Processor Model    : 0x08
Processor Mask     : 0x00
Processor Stepping : 0x06
Feature flags      : 0x0387fbff

Cache/TLB descriptor values: 1 reads required
Desc 0x01 : Instr TLB: 4KB pages, 4-way set assoc, 32 entries
Desc 0x02 : Instr TLB: 4MB pages, fully assoc, 2 entries
Desc 0x03 : Data TLB: 4KB pages, 4-way set assoc, 64 entries
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x00 : null
Desc 0x82 : L2 Unified cache: 256K bytes, 8-way set assoc, 32 byte line size
Desc 0x08 : Inst cache: 16K bytes, 4-way set assoc, 32 byte line size
Desc 0x04 : Data TLB: 4MB pages, 4-way set assoc, 8 entries
Desc 0x0c : Data cache: 16K bytes, 2-way or 4-way set assoc, 32 byte line size

op: 0x03  eax:0x00000000  ebx:0x00000000  ecx:0x4027736e  edx:0x0002ce88


MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Configuring L2 cache...CPU signature of 680 so no L2 cache configuration
Enable Cache
done.
Disabling local apic...done.
CPU #0 Initialized
Allocating PCI resources...COMPUTE_ALLOCATE: do IO
compute_allocate_io: base 0x1000
compute_allocate_io: base 0x1000
DEVIO: Bus 0x2, devfn 0x8, reg 0x1: iosize 0x20
-->set base to 0x1000
DEVIO: Bus 0x2, devfn 0x50, reg 0x0: iosize 0x40
-->set base to 0x1020
BUS 2: set iolimit to 0x1fff
BUSIO: done Bridge Bus 0x2, iobase now 0x2000
compute_allocate_io: base 0x2000
BUS 1: set iolimit to 0x1fff
BUSIO: done Bridge Bus 0x1, iobase now 0x2000
DEVIO: Bus 0x0, devfn 0xf9, reg 0x4: iosize 0x10
-->set base to 0x2000
DEVIO: Bus 0x0, devfn 0xfa, reg 0x4: iosize 0x20
-->set base to 0x2010
DEVIO: Bus 0x0, devfn 0xfb, reg 0x4: iosize 0x10
-->set base to 0x2030
DEVIO: Bus 0x0, devfn 0xfc, reg 0x4: iosize 0x20
-->set base to 0x2040
DEVIO: Bus 0x0, devfn 0xfd, reg 0x0: iosize 0x100
-->set base to 0x2060
DEVIO: Bus 0x0, devfn 0xfd, reg 0x1: iosize 0x40
-->set base to 0x2160
DEVIO: Bus 0x0, devfn 0xfe, reg 0x0: iosize 0x100
-->set base to 0x21a0
DEVIO: Bus 0x0, devfn 0xfe, reg 0x1: iosize 0x80
-->set base to 0x22a0
BUS 0: set iolimit to 0x2fff
COMPUTE_ALLOCATE: do MEM
compute_allocate_mem: base 0x80000000
compute_allocate_mem: base 0x80000000
DEVMEM: Bus 0x2, devfn 0x8, reg 0x2: memsize 0x100000
-->set base to 0x80000000
DEVMEM: Bus 0x2, devfn 0x10, reg 0x0: memsize 0x1000
-->set base to 0x80100000
DEVMEM: Bus 0x2, devfn 0x28, reg 0x0: memsize 0x1000
-->set base to 0x80101000
DEVMEM: Bus 0x2, devfn 0x28, reg 0x1: memsize 0x4000
-->set base to 0x80104000
BUS 2: set memlimit to 0x801fffff
BUSMEM: Bridge Bus 0x2,membase now 0x80200000
compute_allocate_mem: base 0x80200000
DEVMEM: Bus 0x1, devfn 0x0, reg 0x0: memsize 0x1000000
-->set base to 0x81000000
BUS 1: set memlimit to 0x81ffffff
BUSMEM: Bridge Bus 0x1,membase now 0x82000000
BUS 0: set memlimit to 0x81ffffff
COMPUTE_ALLOCATE: do PREFMEM
Compute_allocate_prefmem: base 0x82000000
Compute_allocate_prefmem: base 0x82000000
DEVPREFMEM: Bus 0x2, devfn 0x8, reg 0x0: prefmemsize 0x1000
-->set base to 0x82000000
BUS 2: set prefmemlimit to 0x820fffff
BUSPREFMEM: Bridge Bus 0x2, prefmem base now 0x82100000
Compute_allocate_prefmem: base 0x82100000
DEVPREFMEM: Bus 0x1, devfn 0x0, reg 0x1: prefmemsize 0x8000000
-->set base to 0x88000000
BUS 1: set prefmemlimit to 0x8fffffff
BUSPREFMEM: Bridge Bus 0x1, prefmem base now 0x90000000
DEVPREFMEM: Bus 0x0, devfn 0x0, reg 0x0: prefmemsize 0x4000000
-->set base to 0x90000000
BUS 0: set prefmemlimit to 0x93ffffff
ASSIGN RESOURCES, bus 0
Bus 0x0 iobase to 0x1000 iolimit 0x1fff
Bus 0x0 membase to 0x80000000 memlimit 0x801fffff
Bus 0x0 prefmembase to 0x82000000 prefmemlimit 0x820fffff
Bus 0x0 iobase to 0x2000 iolimit 0x1fff
Bus 0x0 membase to 0x80200000 memlimit 0x81ffffff
Bus 0x0 prefmembase to 0x82100000 prefmemlimit 0x8fffffff
Bus 0x0 devfn 0x0 reg 0x0 base to 0x90000000
Bus 0x0 devfn 0xf9 reg 0x4 base to 0x2001
Bus 0x0 devfn 0xfa reg 0x4 base to 0x2011
Bus 0x0 devfn 0xfb reg 0x4 base to 0x2031
Bus 0x0 devfn 0xfc reg 0x4 base to 0x2041
Bus 0x0 devfn 0xfd reg 0x0 base to 0x2061
Bus 0x0 devfn 0xfd reg 0x1 base to 0x2161
Bus 0x0 devfn 0xfe reg 0x0 base to 0x21a1
Bus 0x0 devfn 0xfe reg 0x1 base to 0x22a1
Bus 0x1 devfn 0x0 reg 0x0 base to 0x81000000
Bus 0x1 devfn 0x0 reg 0x1 base to 0x88000000
Bus 0x2 devfn 0x8 reg 0x0 base to 0x82000000
Bus 0x2 devfn 0x8 reg 0x1 base to 0x1001
Bus 0x2 devfn 0x8 reg 0x2 base to 0x80000000
Bus 0x2 devfn 0x10 reg 0x0 base to 0x80100000
Bus 0x2 devfn 0x28 reg 0x0 base to 0x80101000
Bus 0x2 devfn 0x28 reg 0x1 base to 0x80104000
Bus 0x2 devfn 0x50 reg 0x0 base to 0x1021
done.
Enabling PCI resourcess...DEV Set command bus 0x0 devfn 0x0 to 0x6
DEV Set command bus 0x0 devfn 0x8 to 0x7
DEV Set command bus 0x0 devfn 0xf0 to 0x7
DEV Set command bus 0x0 devfn 0xf8 to 0xf
DEV Set command bus 0x0 devfn 0xf9 to 0x1
DEV Set command bus 0x0 devfn 0xfa to 0x1
DEV Set command bus 0x0 devfn 0xfb to 0x1
DEV Set command bus 0x0 devfn 0xfc to 0x1
DEV Set command bus 0x0 devfn 0xfd to 0x1
DEV Set command bus 0x0 devfn 0xfe to 0x1
DEV Set command bus 0x1 devfn 0x0 to 0x2
DEV Set command bus 0x2 devfn 0x8 to 0x3
DEV Set command bus 0x2 devfn 0x10 to 0x2
DEV Set command bus 0x2 devfn 0x28 to 0x2
DEV Set command bus 0x2 devfn 0x50 to 0x1
done.
HEECHUL: mainboard_fixup Done()
HEECHUL: !defined(MAINBOARD_FIXUP_IN_CHARGE)
Zeroing PCI IRQ settings...done.
Copying IRQ routing tables...done.
Jumping to linuxbiosmain()...

Welcome to elfboot, the open sourced starter.
Febuary 2001, Eric Biederman.
Version 0.99

    72:fill_inbuf() - zkernel_start:0xfff80000  zkernel_mask:0x0000ffff
   101:fill_inbuf() - nvram:0xfff80000  block_count:0
Clearing Section: addr: 0x0000000000097e88 memsz: 0x0000000000002658
Loading Section: addr: 0x0000000000094000 memsz: 0x00000000000064e0 filesz: 
0x0000000000003e88
Jumping to boot code
ROM segment 0xBFF7 length 0xFFFE reloc 0x9400
clocks_per_tick = 629978
Etherboot 5.1.1 (GPL) ELF (Multiboot) for [EEPRO100]
Boot from (N)etwork or from (L)ocal? N
Found Intel EtherExpressPro100 at 0x1000, ROM address 0x0000
Probing...[EEPRO100]
The PCI BIOS has not enabled this device!
Updating PCI command 0003->0007. pci_bus 0002 pci_device_fn 0008
Ethernet addr: 00:90:27:2F:E1:73 
Searching for server (DHCP)...
-\|/-\|/-\|/Me: 129.254.180.119, Server: 129.254.180.120
Loading 129.254.180.120:qplusp.etherboot -\|/-\|HEECHUL: os_download(): elf
(ELF)... /-\|/-\|..../-\    // stop here.. after receiving for some time.

RE: Current state of 815ep port..

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