[EMAIL PROTECTED] writes: > After successful testing linuxbios with my 440bx board, now I'm trying to > port linuxbios to an 815ep board (Gigabyte GA-6OXE). Maybe I'm too brave, I > have trouble just enabling serial. T_T
That is the hardest part.... :) > I thought i can get serial working without any 815ep chipset initialiation > (especially ICH2)because 440bx(maybe other chipset also) does. Am I right? That should be correct. I'm working on a similiar problem, the 860 chipset that also uses the ICH2. As I have read the documentation it doesn't appear to require any initialization. And the path works for BIOS read/writes. The only case where I have encountered the need for initialization was the AMD766 which had both an LPC and an ISA bus. In that case you had to direct writes over which bridge they needed to go. > Therfore, At first, I wrote little initialization code for ITE it8712f > super I/O chip because it is not exist in current cvs tree. Then before > doing raminit.inc I tested serial output with TTYS0_TX_STRING() and do > 'hlt' intruction to stop. However, as you may think, I can't get the > message from serial. I can't contribute much as I am in a similiar fix. Hopefully resolved soon. I have seen watchdog timers cause this kind of problem. The only concrete suggestion I have is that it might be easier to test to see if you are doing something correctly with a POST card. > I think there's 3 possiblity. > 1) ITE it8712ef initialization code which i wrote is wrong. > I wrote this code as described in the data sheet, so i think > there's no problem. But, maybe it is possible i did some stupid > typo > or something so I attached this code. Data sheet can be found at > http://www.ite.com.tw/productInfo/Download.html#IT8712F > > 2) DualBIOS is the problem. > My board comes with physically two same bios installed. gigabyte > says > if one of them fail (both physically and logically mis programmed) > another bios > takes over. They called it as DualBIOS technology. > What I don't know, so I suspect, is how they decide a bios is > failed. > Linuxbios is failed bios? hmm. I mailed to gigabyte about this, but > no response > until now. > > 3) My theory is wrong. ICH2 must be initialized before accessing super i/o > chip. > For now, I don't know much about ICH2, MCH, ... I just printed > their data sheet. :) Absorb the datasheet, and tripple check your code. Mostly all you should need to ensure is that the lpc bus is doing subtractive decode, and your memory access cycles should get there. But it is certainly possible to trace which logic in the chips control this and what their default values are. > Any help, comment, will be very valuable to me. When I make some headway I will let you know. Eric
