"Eric W. Biederman" wrote: > > Ronald G Minnich <[EMAIL PROTECTED]> writes: > > > Fooey. I thought all these were fixed. > > > > LinuxBIOS pci setup is not setting up BARs totally according to PCI spec. > > We are not aligning them correctly. Amazingly enough today is the first > > day this bug caused us any trouble ... symptom was in etherboot, a tulip > > card would not respond to I/O addresses as linuxbios configured BAR 1 to > > 0x1030, it is a 64-byte space and the address needs to be 64-byte > > aligned. > > > > I'll try to get the fix in today. > > Interesting. Given that this is the second fix we have put in recently > to the pci code, counting the nested pci bridge fix, and vga card fix > as one fix. > > It looks like we have reached another level of maturity. We just > got a whole flock of new bugs discovered, and fixed :) > > The truly interesting pci setup trick is when the amount of memory we > setup needs to be reduced to allow room for pci memory regions. This > happens on 4GB+ boxes. > > Eric
While porting to my non-PC 440BX-equipped board, I had to do 3 things: align the IO, worry about nested bridges, and the 3rd was to force the PIIX4 function 3 config regs 40h & 90h into the IO list. These weren't being scanned, but they must be setup. I also see couple non-standard register addresses in the 815 chipset that would not be enumerated by default: device/vendor 24408086 bus/dev/func/reg 0/31/0/40h & 0/31/0/58h. Christopher Stutts Innovative Concepts, Inc. [EMAIL PROTECTED]
