> Hmm. I want to say that is 0x50-0x57... > As I recall the specification for memory dimms only has 3 address > lines you can change. So yes the spd rom must be addressable in the > 0x50-0x57 range, on whatever bus it is on. Ok - Ollie is not so happy with this .... I'll wait for Ron's answer to him ...
> It depends on the instruction. I think it takes a shlc or something > like that. Perhaps we have been getting luck. That's what I wondered .. but apparently not (good :) > As far as I can tell I2C and SMBUS are interrelated standards > targeting slightly different audiences. What I read today suggested that SMBus was the ratified standard from Intel that altered only slightly the already-implimented answer from VIA ... > Right this is one of the more interesting things. Usually a > motherboard will have only one i^2c interface and a mux on the i2c > line to let you select which bus you really want to talk to. > Generally you want to look at the state of the GPIO lines as > those seem to control things like that. Yeah ... I don't quite have the resources for that ... we'll see ... Marcus had a problem with one of the ASUS chipsets (probably due to this). > I have the same issue on the supermicro p4dc6. > > O.k. Now back to my regularly scheduled sleep. Thanks Eric.
